Implementation of 10m multifunctional signal generator with FPGA

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Overall scheme demonstration and selection

Scheme 1 ： Analog phase locked loop is used to realize . Analog phase locked loop technology is a relatively mature technology . Apply analog phase locked loop , The reference frequency can be doubled , Or divide the frequency to get the required frequency , And the adjustment accuracy can be quite high 、 The stability is also good . But the analog circuit of analog phase locked loop is complex , Not easy to adjust , The high cost , And the frequency adjustment is inconvenient and the adjustment range is small , There are many burrs in the output waveform , Can't get satisfactory results .
Option two ： Direct digital frequency synthesis , Single chip microcomputer is used as the core control component . Can meet higher requirements , Realize various waveform output , But it is limited by the number of operation bits and operation speed , The waveform produced is often not satisfactory , And the frequency adjustable range is small , It's hard to get a higher frequency , And the pins of the single chip microcomputer are few , Less storage capacity , This leads to complex peripheral circuits .
Option three ： Direct digital frequency synthesis , use FPGA Device as the core control component . High accuracy and good stability , Get smooth waveform , Especially because FPGA High speed , It can realize higher frequency waveform . It is more convenient to control , Waveform output with a wide frequency range can be obtained , Step small , The peripheral circuit is simple and easy to realize .
After the above analysis , The core control system adopts scheme 3 .

DDS Demonstration of module scheme

Scheme 1 ： High performance DDS Solutions for monolithic circuits .
With the rapid development of microelectronics technology , At present, excellent performance DDS Products continue to launch , There are mainly Qualcomm、AD、Sciteg and Stanford And so on （monolithic）.Qualcomm The company launched DDS series Q2220、Q2230、Q2334、Q2240、Q2368, among Q2368 The clock frequency of is 130MHz, A resolution of 0.03Hz, The frequency conversion time is 0.1μs; The United States AD Companies have also launched their DDS series ：AD9850、AD9851、 It can realize linear frequency modulation AD9852、 Two orthogonal outputs AD9854 As well as DDS Core QPSK Modulator AD9853、 Digital up converter AD9856 and AD9857.AD The company's DDS Series products with its high performance price ratio , At present, it has been widely used .
Option two ： Low frequency sine wave DDS Solutions for monolithic circuits
The typical circuits of this scheme are MicroLinear The power management division of the company launched low-frequency sine wave DDS Monolithic circuit ML2035 With its low price 、 Easy to use, widely used .ML2035 characteristic ：（1） The output frequency is DC to 25kHz, The clock input is 12.352MHz The external frequency resolution can reach 1.5Hz（-0.75～+0.75Hz）, Peak of output sine wave signal - The peak value is Vcc;（2） Highly integrated , No or very little external component support , Bring their own 3～12MHz Crystal oscillation circuit ;（3） Compatible 3 Line SPI Serial input port , With double buffer , It can be conveniently used with single chip microcomputer ;（4） Gain error and total harmonic distortion are very low .ML2035 The frequency of generation is low （0～25kHz）, It is generally used in some occasions where the frequency to be generated is power frequency and audio . If used 2 slice ML2035 Generate multi frequency mutual control signal , And with AMS3104（ Multi frequency receiving chip ） or ML2031/2032（ Audio detector ） coordination , Make the transceiver circuit in the communication system . Programmable Sine wave generator chip ML2035 Clever design , Programmable 、 Easy to use 、 Low price and other advantages , A wide range of applications . Very suitable for low cost 、 Occasions with high reliability of low-frequency sine wave signals .
Option three ： Self designed based on CPLD/FPGA Chip solutions
DDS The realization of technology depends on high speed 、 High performance digital devices . Programmable logic device with its high speed 、 Large scale 、 Online programmable , And strong EDA Software support and other features , It is very suitable for realizing DDS technology . at present PLD device （ Include CPLD、FPGA） The main manufacturers are Altera,Xilinx as well as Lattoce etc. .Altera It's famous PLD Manufacturer , It has been occupying a leading position in the industry for many years .Altera Of PLD High performance 、 Advantages of high integration and high cost performance , In addition, it also provides comprehensive development tools and rich IP nucleus 、 Besides macro functions, it also provides comprehensive development tools and rich IP nucleus 、 Macro library, etc , therefore Altera Our products have been widely used . Although some are dedicated DDS The chip also has many functions , But the control mode is fixed , Therefore, it is not necessarily what we need . And the use of FPGA You can conveniently realize various complex frequency modulation according to your needs 、 Phase modulation and amplitude modulation function , It has good practicability . In terms of synthetic signal quality , special DDS The chip adopts specific integration process , The internal digital signal jitter is very small , It can output high-quality analog signals ; utilize FPGA It can also output high-quality signals , Although it can't reach the special purpose DDS The level of the chip , But the signal accuracy error is within the allowable range .
Based on the above advantages, we adopt FPGA Chip to realize our design DDS.

Overall design block diagram

The basic principle of direct digital frequency synthesis technology

Verilog HDL Code implementation and simulation

Signal generator module

Frequency control word and phase accumulator

Bits of bit accumulator N=32,Verilog HDL The code is as follows ：

1.module F_word_set(
2. input    clk  ,
3. input    rst_n ,
4. input    key1_in ,
5.
6. output reg [25:0] f_word 
7. );
8. 
9. wire  key_flag ;
10. wire  key_state ;
11. reg [3:0] cnt   ;
12.
13. key_filter fword_key (
14.   .clk       (clk),
15.   .rst_n     (rst_n),
16.   .key_in    (key1_in),
17.   .key_flag  (key_flag),
18.   .key_state (key_state)
19.  );
20.
21. always @(posedge clk or negedge rst_n) begin
22.  if (!rst_n) begin
23.   cnt <= 4'd0;
24.  end
25.  else if (key_flag) begin
26.   if (cnt==4'd10) begin
27.    cnt <= 4'd0;
28.   end
29.   else begin
30.    cnt <= cnt + 1'b1;
31.   end
32.  end
33. end
34.
35. always @(posedge clk or negedge rst_n) begin
36.  if (!rst_n) begin
37.   f_word <= 0;
38.  end
39.  else begin
40.   case(cnt)
41.    4'd0:f_word = 26'd86;  //1Hz
42.    4'd1:f_word = 26'd859;  //10Hz
43.    4'd2:f_word = 26'd8590;  //100Hz
44.    4'd3:f_word = 26'd42950; //500Hz
45.    4'd4:f_word = 26'd85899; //1kHz
46.    4'd5:f_word = 26'd429497; //5kHz
47.    4'd6:f_word = 26'd858993; //10kHz
48.    4'd7:f_word = 26'd4294967; //50kHz
49.    4'd8:f_word = 26'd8589935; //100kHz
50.    4'd9:f_word = 26'd17179869; //200kHz
51.    4'd10:f_word = 26'd42949673;//500kHz
52.    default:;
53.   endcase
54.  end
55. end
56.endmodule