当前位置:网站首页>Basic knowledge of trigger (Part 2)

Basic knowledge of trigger (Part 2)

2022-07-24 02:55:00 Li Yuchen

 Insert picture description here

Welcome to learn digital circuit ——D trigger .

Here we will explain D Triggers and integration edges D trigger 74LS74, I hope that through our study, you will better understand the mystery of digital circuits .

Catalog

  One 、D trigger

1.D The circuit composition and logic function of the trigger

(1) Circuit structure and graphical symbols

(2) logic function

2. Integrated edge D trigger

(1) Pin arrangement and graphical symbols

(2) logic function

Two 、 Trigger knowledge dry goods


  One 、D trigger

1.D The circuit composition and logic function of the trigger

(1) Circuit structure and graphical symbols

As shown in the figure :

  In sync RS Based on the trigger , NAND gate G3 Output \overline{S} Receive the NAND gate G4 The input of R, send R=\overline{S}, Thus avoiding \overline{S}=\overline{R}=0 The situation of . And will NAND gate G3 Of S End changed to D Input end , That is to say D trigger .

(2) logic function

D A trigger has only one input , Eliminate the indefinite state of the output .D The trigger has a set 0、 Set up 1 The logical function of , As shown in the figure :

  It can be seen from the picture that ,

stay CP=0 period :

NAND gate G3、G4 By CP The low level of the terminal is off , Disable the input signal ,\overline{S}=\overline{R}=1, basic RS The trigger remains in its original state .

stay CP=1 period :

① Set up 0 function

When D=0 when , NAND gate G3 Output \overline{S}=1、G4 Output \overline{R}=0, Basically RS The trigger output is set to 0.

② Set up 1 function

When D=1 when ,  NAND gate G3 Output \overline{S}=0、G4 Output \overline{R}=1, Basically RS The trigger output is set to 1.

As shown in the figure :

  In the 3 individual CP During pulse action , because D The change of causes the state of the trigger to change many times , There is somersault , send CP The pulse loses the meaning of synchronization . So in practice , Often use edges D trigger .

Next, let's learn the last trigger : Integrated edge D trigger .

2. Integrated edge D trigger

(1) Pin arrangement and graphical symbols

74LS74 The chip is Integrated double rising edge D trigger , As shown in the figure :

 CP It is the clock input ;D For data input ;Q、\overline{Q} Complementary output ;\overline{R_{D}} It is the direct reset end , Low level active ;\overline{S_{D}} It is the direct setting end , Low level active ;\overline{R_{D}} and \overline{S_{D}} Used to set the initial state .

(2) logic function

As shown in the table , Is the integrated double rising edge D trigger 74LS74 My menu , In the table “↑” Indicates that the rising edge triggers .

 \overline{R_{D}}\overline{S_{D}} It is often used as the initial state of setting trigger . Integrate D The logic function of the trigger is the same as that described above D Triggers are basically the same , The difference is that it only CP Working at the rising edge .

Two 、 Trigger knowledge dry goods

 


That's all for the trigger , In the next issue, we will continue to explain the sequential logic circuit !🥰🥰 

原网站

版权声明
本文为[Li Yuchen]所创,转载请带上原文链接,感谢
https://yzsam.com/2022/204/202207222351214294.html