VHDL design

Libraries and packages （packages）

Declare constants that will be used in the design or entity , data type

Entity （Entities）

Declare interfaces to entities and designs , That is to define the input of this design 、 Out port

Structure （Architectures）

Defines the implementation of entities . That is, the specific description of the circuit

Or gate

LIBRARY IEEE;                -- library , Package calls 
USE IEEE.STD_LOGIC_1164.ALL
ENTITY MYORY2 IS             -- Entity MYORY2 describe 
    PORT(A,B:IN STD_LOGIC;
         C  :OUT STD_LOGIC);
END MYORY2;
ARCHITECTURE ART1 OF MYOR2 IS
BEGIN                         -- Description of structure 
    C<=A OR B;
END ART1;

  Half adder

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL
ENTITY H_ADDER IS                  -- Entity H_ADDER describe 
    PORT(A,B:IN STD_LOGIC;
         CO,SO:OUT STD_LOGIC);
END H_ADDER;
ARCHITECYURE ART2 OF H_ADDER IS    -- Description of structure 
BEGIN
    SO<=(A OR B)AND(A NAND B);
    CO<=NOT(A NAND B);
END ART2;

Full adder

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITYY F_ADDER IS             -- Entity F_ADDER describe 
    PORT(AIN,BIN,CIN:IN STD_LOGIC;
        CY,SUM:OUT:OUT  STD_LOGIC);
END F_ADDER;
ARCHITECTURE ART3 OF F_ADDER IS
    COMPONENT H_ADDER          -- Component call declaration 
        PORT(A,B:IN STD_LOGIC;
             CO,SO:OUT STD_LOGIC);
     END COMPONENT;
    COMPONENT MYOR2
        PORT(A,B:IN STD_LOGIC;
             C:OUT STD_LOGIC);
    END COMPONENT;
    SIGNAL D,E,F:STD_LOGIC;    -- Signal declaration 
BEGIN
    U1:H_ADDER PORT MAY(A=>AIN,B=>BIN
                        CO=>D,SO=>E);
    U2:H_ADDER PORT MAY(A=>E,B=>CIN,
                        CO=>F,SO=>SUM);
    U3:OR2 PORT MAY(A=>D,B=>F,C=>CY);
END ART3;