Design and simulation code of 4-bit subtracter based on FPGA

1. The design requirements ：

　　 To design a 4 Bit subtractor , Adopt structural design . The design is called sub_4bit, The top-level design is shown in the figure below , There are three inputs ： minuend x[3:0], Subtract y[3:0], Borrowing from low position to standard bin; There are two output standard deviations dif[3:0], Borrowing from standard to high position bout. The mathematical expression is ：(x + bout) – y – bin = diff

 

2. Design implementation

　　4 The bit subtracter consists of four full subtracters ,1 Bit full subtracter consists of two half subtracters and 1 Or doors , As shown in the figure below .

（1） Half subtracter ：

　　 Half subtracter is used to calculate two binary numbers x and y My sword , Output results d And borrow from the high position bo, There is no consideration of borrowing from low to standard .

 

（2） Full subtractor

　　 The full adder has three inputs ： minuend Ai, Subtract Bi, Borrowing from low position to standard Ci-1; There are two output standard deviations Si, Borrowing from standard to high position Ci. The truth table is as follows ：