Verilog size and +: Using

module test;

    reg [7:0] vect_1; 
    reg [0:7] vect_2;
    
    initial
    begin
        vect_1 = 'b0001_1010;
        vect_2 = 'b0010_0010;

        $display("vect_1[3] = %b, vect_2[3] = %b", vect_1[3], vect_2[3]);
        $display("vect_1[7:0] = %b, vect_2[0:7] = %b", vect_1, vect_2);
        $display("vect_1[4+:3] = %b, vect_1[4-:3] = %b", vect_1[4+:3], vect_1[4-:3]); 
        $display("vect_2[4+:3] = %b, vect_2[4-:3] = %b", vect_2[4+:3], vect_2[4-:3]); 
        
        // vect_1[3] = 1, vect_2[3] = 0
        // vect_1[7:0] = 00011010, vect_2[0:7] = 00100010
        // vect_1[4+:3] = 001, vect_1[4-:3] = 110
        // vect_2[4+:3] = 001, vect_2[4-:3] = 100        
        
        $stop;
    end

endmodule