Imx6dl4.1.15 supports EIM bus (upper) - actual operation and modification.

When you meet a customer at work, you need to pass IMX6DL Of EIM Bus and fpga signal communication . You need to configure a 8 Digit bit ,5 Bit address bit EIM Bus .

Feiling 6DLlinux4.1.15 No configuration by default EIM Bus . Need to add EIM Bus configuration , actually , It is similar to adding a serial port , The same three steps ：1、 add to EIM Bus node 2、 Configure pin reuse 3、 Remove other pin functions for reuse .

One 、 First, add nodes .
1、arch/arm/boot/dts/imx6qdl-sabresd.dtsi Add the following to the file

&weim {
    
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_weim_fpga &pinctrl_weim_cs0>;
        #address-cells = <2>;
        #size-cells = <1>;
        ranges = <0 0 0x08000000 0x08000000>;
        status = "disabled"; /* pin conflict with SPI NOR */
       fsl,weim-cs-gpr = <&gpr>;

        [email protected],0 {
    
                compatible = "fpga-user";
                reg = <0 0 0x08000000>;
                #address-cells = <1>;
                #size-cells = <1>;
                bank-width = <2>;
                fsl,weim-cs-timing = <0x00640081 0x00000010 0x1c020000
                                0x0000c000 0x1404a38e 0x00000000>;
        };
};

by eim Some configuration information of the bus .
2、arch/arm/boot/dts/imx6dl-c-sabresd.dts Add... To the file weim Node control .

&weim {
    
       status = "okay";
};

Add one weim Node control , And set its status to okay.

Two 、 Add pin configuration
arch/arm/boot/dts/imx6qdl-sabresd.dtsi Add a fpga Of pinctrl And a cs Pin pinctrl. This part is in the first step weim Nodes in the pinctrl-0 Parameters for these two pinctrl Have call . The corresponding name .

 pinctrl_weim_fpga: weimfpgagrp {
    
                        fsl,pins = <
                                MX6QDL_PAD_EIM_OE__EIM_OE_B             0xb0b1
                                MX6QDL_PAD_EIM_RW__EIM_RW               0xb0b1
                                MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B         0xb060
                                MX6QDL_PAD_EIM_DA5__EIM_AD05            0xb0b1
                                MX6QDL_PAD_EIM_DA4__EIM_AD04            0xb0b1
                                MX6QDL_PAD_EIM_DA3__EIM_AD03            0xb0b1
                                MX6QDL_PAD_EIM_DA2__EIM_AD02            0xb0b1
                                MX6QDL_PAD_EIM_DA1__EIM_AD01            0xb0b1
                                MX6QDL_PAD_EIM_DA0__EIM_AD00            0xb0b1
                                MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00     0xb0b1 
                                MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01       0xb0b1
                                MX6QDL_PAD_CSI0_DAT4__EIM_DATA02        0xb0b1
                                MX6QDL_PAD_CSI0_DAT5__EIM_DATA03        0xb0b1
                                MX6QDL_PAD_CSI0_DAT6__EIM_DATA04        0xb0b1
                                MX6QDL_PAD_CSI0_DAT7__EIM_DATA05        0xb0b1
                                MX6QDL_PAD_CSI0_DAT8__EIM_DATA06        0xb0b1
                                MX6QDL_PAD_CSI0_DAT9__EIM_DATA07        0xb0b1
                               
                        >;
                };

                pinctrl_weim_cs0: weimcs0grp {
    
                        fsl,pins = <
                                MX6QDL_PAD_EIM_CS0__EIM_CS0_B           0xb0b1
                        >;
                };

3、 ... and 、 Remove other multiplexing functions of the used pins .

  pinctrl_i2c1: i2c1grp {
    
                        fsl,pins = <
-                               MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b8b1
-                               MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b8b1
+                       /*      MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b8b1
+                               MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b8b1      */
                        >;
                };
 
@@ -1097,10 +1127,10 @@
                                MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x80000000
                                MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x80000000
                                MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x80000000
-                               MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
-                               MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
+                               //MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
                                MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x80000000
                                MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x80000000
-                               MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x80000000
+                               //MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x80000000
                                MX6QDL_PAD_SD1_DAT2__GPIO1_IO19            0x80000000
                                MX6QDL_PAD_SD1_DAT0__GPIO1_IO16            0x80000000
                                MX6QDL_PAD_GPIO_2__GPIO1_IO02              0x80000000

At this time EIM Debugging , By connecting fpga For example . So the following is to add fpga The process of ：
First you need to add one fpga The driver , This is prepared in advance , Add to /drvier/misc Under the table of contents . And then modify misc Under the Makefile：

 obj-$(CONFIG_ECHO)             += echo/
 obj-$(CONFIG_VEXPRESS_SYSCFG)  += vexpress-syscfg.o
 obj-$(CONFIG_CXL_BASE)         += cxl/
+obj-y                       += fpga.o

add fpga.o The compilation requirements of .
Compile after adding , burning .
View information after startup .
[email protected]:~# dmesg | grep weim
[ 0.356060] imx-weim 21b8000.weim: Driver registered.

[email protected]:~# dmesg | grep fpga
[ 1.500836] imx6q-fpga
[ 1.513477] imx6q-fpga 8000000.fpga: FPGA Driver registered.
The above message appears , explain eim Bus and fpga The drivers are mounted normally .
And check /dev There are fpga node .
Use the test script to test ：
[email protected]:~# ./fpga_test write
[ 244.739123] done the fram_open
[ 244.743919] begain the fram_write
[ 244.747259] done the fram_write
[ 245.750637] begain the fram_write
[ 245.754091] done the fram_write
[ 246.757442] begain the fram_write
[ 246.760781] done the fram_write

[email protected]:~# ./fpga_test read
[ 258.910519] done the fram_open
[ 258.913744] begain the fram_read
[ 258.916994] addr=0x1-------183-----
[ 258.920497] addr=0x1<<1-------183-----
[ 258.924779] addr=0x3FFFFF<<1-------183-----
[ 258.928988] begain the fram_read
[ 258.932232] addr=0x1-------183-----
[ 258.935804] addr=0x1<<1-------183-----
[ 258.939573] addr=0x3FFFFF<<1-------183-----
[ 258.943845] begain the fram_read
[ 258.947094] addr=0x1-------183-----
[ 258.950596] addr=0x1<<1-------183-----
[ 258.954400] addr=0x3FFFFF<<1-------183-----
[ 258.958602] begain the fram_read
[ 258.961845] addr=0x1-------183-----
[ 258.965432] addr=0x1<<1-------183-----
[ 258.969203] addr=0x3FFFFF<<1-------183-----
The response pin has waveform by oscilloscope . It indicates that the bus works normally ：

thus EIM Bus debugging is completed , The rest and fpga The customer needs to solve the problem of equipment joint commissioning .