This usage, SystemVerilog syntax

`timescale 1ns/1ps

// Define variable name  
logic [3:0] DIV_CLKA;
...
logci [3:0] DIV_CLKD;

// Defining classes 
class pll_params;
    rand bit[3:0] refclk_div;
    ...
    rand bit[5:0] div_clk_6bit;
    // Defining variables 
    int ref_clk;
    
    function set_refclk(int ref_clk); //ref_clk Call parameters 
        this.ref_clk = ref_clk;
    endfunction

    function new(int seed);
        this.srandom(seed);
    endfunction

    constraint c{
    
        if(this.ref_clk>200){
            div_clk_6bit ==6`b0;
        } 
        else{
            ...
        }
    }
    
endclass

In the class function、task、constraint Use in class The variables inside , You need to precede the variable with this. marked . Be careful ： use this, Whether it has the same name with parameters and variables , It doesn't matter.