Single cycle CPU of the design group of West University of Technology

One cycle CPU

Words csdn Why not directly from md Document import pictures , I had to manually put the picture for half a day

---

1. The experimental requirements

• Use verilog Hardware description language design a single cycle cpu
• Complete the basic module design
• complete addu Verification of instructions
• complete R Verification of type I instructions
• complete I Verification of type I instructions
• complete MEM Verification of type I instructions
• complete J Verification of type I instructions

2. Experimental process

2.1 Basic modules

2.1.1 PC modular

Basic function

Used to update the current instruction address , When reset The signal is low level , Then initialize pc, Otherwise, accept npc

Module signal

Signal name	Direction	describe
clock	I	Clock signal
reset	I	Reset signal
npc	I	Next instruction address
pc	O	Current instruction address

Module code

module pc(pc,clock,reset,npc);

output reg [31:0] pc;// Current instruction address 

input clock;

input reset;

input [31:0] npc;// The next one pc Instruction address 

[email protected](posedge clock,negedge reset )


begin
    if(!reset)//reset Low level initializes PC, Otherwise, accept the new address 
    begin
        pc<=32'h0000_3000;
    end
    else
    begin
        pc<=npc;
    end
    
end

endmodule

2.1.2 IM modular

Basic function

For reading instructions , Instruction memory is utilized by direct reading MARS Assemble the text file to get the instructions to be executed

$readmemh("code.txt",S_CYCLE_CPU.IM.ins_memory)

im Input address of the module pc yes 32 position , But instruction memory ins_memory Only 4kB（ namely 1KW）, So take pc It's low 12 as ins_memory The address of . On the other hand , although MIPS Instructions are of fixed length 32 position （ One word ）, however MIPS Is addressed by bytes , So the word address is pc>>2

Module signal

Signal name	Direction	describe
pc	I	Address
instruction	O	Instructions

Module code

module im(instruction,pc);

output [31:0] instruction;

input [31:0] pc;

reg [31:0] ins_memory[1023:0]; //4k Instruction memory ;

assign instruction=ins_memory[pc[11:0]>>2];

endmodule

2.1.3 gpr modular

Module function

Register heap implements MIPS In the instruction set 32 A register

Module signal

Signal name	Direction	describe
clock	I	Clock signal
rs	I	Read register 1 The address of
rt	I	Read register 2 The address of
num_write	I	Write the address of the register
data_write	I	Write the contents of the register
reg_write	I	Write enable signal
a	O	Read register 1 The content of
b	O	Read register 2 The content of

Module code

module gpr(a,b,clock,reg_write,num_write,rs,rt,data_write);

output reg [31:0] a;  

output reg [31:0] b;

input clock;// Clock signal 

input reg_write;// Write enable signal 

input [4:0] rs; // Read register 1

input [4:0] rt; // Read register 2

input [4:0] num_write; // Write register 

input [31:0] data_write; // Writing data 

reg [31:0] gp_registers[31:0];  //32 A register 

always @(posedge clock)
begin
    if(reg_write)
        gp_registers[num_write]<=data_write;
    else
        gp_registers[num_write]<=gp_registers[num_write];
end

// Make 0 The position is always 0
always @(*)
begin
    gp_registers[0]<=32'b0;
end
[email protected](*)begin
a=(rs==5'b0)?32'b0:gp_registers[rs];
b=(rt==4'b0)?32'b0:gp_registers[rt];
end

endmodule

2.1.4 alu modular

Module function

Implement various operations , Such as addition , Subtraction , Or sum operation, etc , And output the results and 0 Sign a

Module signal

Signal name	Direction	describe
a	I	Operands 1
b	I	Operands 2
aluop	I	opcode
c	O	The result of the calculation is
zero	O	Zero signal , For branch instructions

Module code

`include "ctrl_encode_def.v"
module alu(c,
           a,
           b,
           aluop);
    
    
    
    output reg [31:0] c;
    
    input [31:0] a;
    input [31:0] b;
    input [3:0] aluop;
    [email protected](a or b or aluop)
    begin
        case(aluop)
        `ALUOp_ADDU:c=a+b; //ADDU
        `ALUOp_SUBU:c=a-b; //SUBU
        `ALUOp_ADD: c=$signed(a)+$signed(b);
        `ALUOp_AND:  c = a & b;                    // AND/ANDI
        `ALUOp_OR:   c = a | b;                    // OR/ORI
        `ALUOp_SLT:  c = ($signed(a) < $signed(b)) ? 32'd1 : 32'd0;  // SLT/SLTI
        default: c=32'd0;
        endcase
    end
    
    
endmodule

2.1.5 dm modular

Module function

Used to read and write data , When write enable is effective , Write data by address , When the read is valid , Read and fetch data according to the address .

Module signal

Signal name	Direction	describe
clock	I	Clock signal
address	I	Address
data_in	I	data input
mem_write	I	Write enable signal
data_out	O	Data output

Module code

module dm(data_out,
          clock,
          mem_write,
          address,
          data_in);
    
    output [31:0] data_out;
    
    input clock;
    
    input mem_write;
    
    input [31:0] address;
    
    input [31:0] data_in;
    
    reg [31:0] data_memory[1023:0]; //4K Data storage 
    
    
    assign data_out = data_memory[address[11:2]];
    
    [email protected](posedge clock )
    begin
        if(mem_write)
            data_memory[address[11:2]] <= data_in;
    end
endmodule

2.1.6 npc modular

Module function

Calculate the address of the next instruction

Module signal

Signal name	Direction	describe
pc	I	Current instruction address
npc	O	Next instruction address
Imm26	I	Input 26 digit
pc_gpr	I	Address obtained from register
s_npc	I	Select signal
zero	I	0 Sign a

Module code

`include "ctrl_encode_def.v"
module npc(pc,
           npc,
           Imm26,
           pc_gpr,
           s_npc,
           zero);
    input [31:0] pc;
    input zero;
    output reg [31:0] npc;
    input [25:0] Imm26;
    input [1:0] s_npc;
    input [31:0] pc_gpr;
    reg [31:0] temp1;
    [email protected](*)
    begin
    temp1={
   {16{Imm26[15]}},Imm26[15:0]}<<2;
    end
    
    
    [email protected](*)
    begin
        case(s_npc)
            `PC_J:
            begin
                npc = {pc[31:28],Imm26,2'b00};
            end
            `PC_JR:
            begin
                npc = pc_gpr;
            end
            `PC_BEQ:
            begin
              npc = zero?pc+4+temp1:pc+4;
            end
            `PC_4:
            npc = pc+4;
        endcase
    end
    
endmodule

2.1.7 ctrl modular

Module function

According to the input instruction field , Get the control signal , To control alu,dm,gpr Etc

Module signal

Signal name	Direction	describe
aluop	O	control alu The signal of
s_b	O	Select immediate or register value as alu The input of
s_num_write	O	Select the data to write to the register file
reg_write	O	Register heap write enable signal
s_ext	O	Immediate spread signal
s_data_write	O	Select the data to write to the register
mem_write	O	Memory write enable signal
s_npc	O	pc Select signal
op	I	Signal type
funct	I	Function code signal
pc	I	At present pc

Module code

`include "ctrl_encode_def.v"
module ctrl(aluop,
            op,
            funct,
            s_b,
            s_num_write,
            reg_write,
            s_ext,
            pc,
            mem_write,
            s_data_write,
            s_npc
            );
    output reg [3:0] aluop;//aluop Represents six basic operation flag signals 
    output reg s_b;// Select data storage alu The source operation of 1�72 1 by b＄1�70 by Imm_32
    output reg [1:0] s_num_write;// Select the number stored in the write register 1�7 1 by rt 0 by rd 2 A kind of 1�731
    output reg reg_write;// Write enable signal ,1 Valid for writing ＄1�70 Invalid for write 
    output reg s_ext;// Select the extension method  1 Expand symbol 1�7 0 Expand the zero bit 1�7
    output reg [1:0] s_data_write;// Select register to write  1 by dm＄1�70 by alu
    output reg mem_write;// Data store write enable signal ＄1�71 To be able to write ,0 Why not write brother 1�7
    output reg [1:0] s_npc;
    input wire [5:0] op;
    input [5:0] funct;
    input  [31:0] pc;
    
    [email protected](op,funct)
    begin
        if (op == 6'b000000)
            if(funct==`JR)
            begin
            s_npc=`PC_JR;
            end
            else
            begin
            s_num_write=`NUM_WRITE_RD;reg_write=1;mem_write=0;    
            aluop = funct[3:0];s_b=`ALU_GPR;s_npc=`PC_4;s_data_write=`MEM_ALU;
            end
        else
            case(op)
            `ALUOp_ADDI:
            begin 
            aluop=`ALUOp_ADD;s_b=0;s_ext=1;s_num_write=`NUM_WRITE_RT;
            reg_write=1;mem_write=0;s_data_write=`MEM_ALU;s_npc=`PC_4;
            end
            `ALUOp_ADDIU:
            begin 
            aluop=`ALUOp_ADDU;s_b=0;s_ext=1;s_num_write=`NUM_WRITE_RT;
            reg_write=1;mem_write=0;s_data_write=`MEM_ALU;s_npc=`PC_4;
            end
            `ALUOp_ANDI:
            begin 
            aluop=`ALUOp_AND;s_b=0;s_ext=0;s_num_write=`NUM_WRITE_RT;
            reg_write=1;mem_write=0;s_data_write=`MEM_ALU;s_npc=`PC_4;
            end
            `ALUOp_ORI:
            begin 
            aluop=`ALUOp_OR;s_b=0;s_ext=0;s_num_write=`NUM_WRITE_RT;
            reg_write=1;mem_write=0;s_data_write=`MEM_ALU;s_npc=`PC_4;
            end
            `ALUOp_LUI:
            begin
            aluop=`ALUOp_LU;s_b=0;s_ext=0;s_num_write=`NUM_WRITE_RT;
            reg_write=1;mem_write=0;s_data_write=`MEM_ALU;s_npc=`PC_4;
            end
            `ALUOp_SW:
            begin
            aluop=`ALUOp_ADDU;s_b=0;s_ext=1;s_num_write=`NUM_WRITE_RT;
            reg_write=0;mem_write=1;s_data_write=`MEM_ALU;s_npc=`PC_4;
            end
            `ALUOp_LW:
            begin
            aluop=`ALUOp_ADDU;s_b=0;s_ext=1;s_num_write=`NUM_WRITE_RT;
            reg_write=1;mem_write=0;s_data_write=`MEM_MEM;s_npc=`PC_4;
            end
            `J:
            begin
            s_npc=`PC_J;
            end
            `JAL:
            begin
            s_npc=`PC_J;s_data_write=`MEM_PC;

            end
            `BEQ:
            begin
            aluop=`ALUOp_SUBU;s_b=`ALU_GPR;s_npc=`PC_BEQ;

            end
            endcase
    end
    
    
    
endmodule

2.1.8 ext modular

Module function

take 16 The number of digits is extended to 32 digit , You can choose 0 Extensions or symbolic extensions

Module signal

Signal name	Direction	describe
s_ext	I	Extended format selection
Imm16	I	16 Immediately
Imm32	I	32 Immediately

Module code

module ext(
    input s_ext,//1 Is for signed extensions ,0 Is an unsigned extension 
    input [15:0] Imm16,
    output reg [31:0] Imm32
);

[email protected](Imm16)
begin
if(s_ext==1)
Imm32={
   {16{Imm16[15]}},Imm16};
else
Imm32={
   {16{1'b0}},Imm16};
end


endmodule //ext

2.1.9 mux_2_32 modular

Module function

Select input alu Is the data of a register or an immediate number

Module signal

Signal name	Direction	describe
s_b	I	Select input alu The data of
b	I	Data read from register
Imm32	I	32 Immediately
alu_in	O	Input alu The data of

Module code

`include "ctrl_encode_def.v"
module mux_2_32 (
	input s_b,
	input [31:0] b,
	input [31:0] Imm32,
	output reg [31:0] alu_in
	
);

[email protected](*)
begin
case(s_b)
`ALU_GPR:
alu_in=b;
`ALU_IMM:
alu_in=Imm32;
endcase

end

endmodule //mux_2_32

2.1.10 mux_3_5 modular

Module function

choice alu Write register of

Module signal

Signal name	Direction	describe
s_num_write	I	Select signal
rt	I	Input rt Field
rd	I	Input rd Field
imm	I	Enter an immediate number
num_write	O	Finally selected data

Module code

`include "ctrl_encode_def.v"
module mux_3_5 (
    input [1:0] s_num_write,//1ʱѡÔñrt,0ʱѡÔñrd
    input [4:0] rt,
    input [4:0] rd,
    input [4:0] imm,
    output reg [4:0] num_write
    
);

[email protected](*)
begin
    case(s_num_write)
    `NUM_WRITE_RT:
    num_write=rt;
    `NUM_WRITE_RD:
    num_write=rd;
    `NUM_WRITE_IMM:
    num_write=imm;
    endcase

end

endmodule //mux_

2.1.11 mux_3_32 modular

Module function

According to the selection signal , Select the data finally written to the register

Module signal

Module name	Direction	describe
alu_out	I	come from alu The data of
mem_out	I	Data from the data store
pc_in	I	pc+4
select	I	Select signal
data	O	Finally selected data

Module code

`include "ctrl_encode_def.v"
module mux_3_32 (
	input [31:0] alu_out,
	input [31:0] mem_out,
	input [31:0] pc_in,
	input [1:0] select,
	output reg [31:0] data
	
);
[email protected](*)
begin
case(select)
`MEM_ALU:
data=alu_out;
`MEM_MEM:
data=mem_out;
`MEM_PC:
data=pc_in;
endcase
end

endmodule //mux_3

Module code

`include "ctrl_encode_def.v"
module mux_3_32 (
	input [31:0] alu_out,
	input [31:0] mem_out,
	input [31:0] pc_in,
	input [1:0] select,
	output reg [31:0] data
	
);
[email protected](*)
begin
case(select)
`MEM_ALU:
data=alu_out;
`MEM_MEM:
data=mem_out;
`MEM_PC:
data=pc_in;
endcase
end

endmodule //mux_3 

2.1.12 s_cycle_cpu modular

Module function

Integrate each module , Implement data path , And according to different requirements to be realized , Reasonably design the signal name .

Here we take the final design as an example

The data path is

Module signal

Signal name	Direction	describe
clock	I	Clock signal
reset	I	Reset signal

Module code

module s_cycle_cpu(clock,
                   reset);
    
    //ÊäÈë
    
    input clock;
    
    input reset;
    
    wire [31:0] pc;
    wire [31:0] npc;
    pc PC(.clock(clock),.reset(reset),
    .pc(pc),
    .npc(npc));
    // assign npc=pc+4;
    wire [31:0] instruction;
    
    im IM(.pc(pc),
    .instruction(instruction));

    wire [31:0] a;
    wire [31:0] b;
    wire [31:0] c;
    wire reg_write;
    // assign reg_write=1;
    wire s_ext;
    wire s_b;
    wire [1:0] s_num_write;
    wire [31:0] Imm32;
    wire [4:0] num_write;
    wire [31:0] b_out;
    wire [4:0] rt;
    assign rt=instruction[20:16];
    wire [5:0] op;
    assign op=instruction[31:26];

    wire [31:0] data_write;
    wire mem_write;
    wire [1:0] s_data_write;
    wire [1:0] s_npc;
    wire [31:0] data_out;
    wire [3:0] aluop;
    wire zero;
    
    gpr GPR(.a(a),.b(b),.clock(clock),
    .reg_write(reg_write),.num_write(num_write),
    .rs(instruction[25:21]),.rt(rt),
    .data_write(data_write));


    alu ALU(.a(a),.b(b_out),.c(c),.aluop(aluop),.zero(zero));
    

    ctrl CTRL(.pc(pc),.s_ext(s_ext),.s_b(s_b),.s_num_write(s_num_write),
    .aluop(aluop),.op(op),.funct(instruction[5:0]),.reg_write(reg_write)
    ,.mem_write(mem_write),.s_data_write(s_data_write),.s_npc(s_npc));

    ext EXT(.s_ext(s_ext),.Imm16(instruction[15:0]),.Imm32(Imm32));

    mux_3_5 MUX_3_5(.s_num_write(s_num_write),.rt(rt),.rd(instruction[15:11])
    ,.imm(5'b11111),.num_write(num_write));
    mux_2_32 MUX_2_32(.s_b(s_b),.b(b),.Imm32(Imm32),.alu_in(b_out));

    mux_3_32 MUX_3_32(.alu_out(c),.mem_out(data_out),.pc_in(pc+4),
    .select(s_data_write),.data(data_write));

    npc NPC(.pc(pc),.npc(npc),.Imm26(instruction[25:0]),
    .pc_gpr(a),.s_npc(s_npc),.zero(zero));

    dm DM(.address(c),.clock(clock),.data_in(b),
    .mem_write(mem_write),.data_out(data_out));
    
    
endmodule

2.1.13ctrl_encode_def Macro definition

This file defines some used signal values

Using this method , Easy to write code , Analysis of the code

// 
`define JR 6'b001000
`define J 6'b000010
`define JAL 6'b000011
`define BEQ 6'b000100

// ALU control signal
`define ALUOp_ADDU  4'b0001
`define ALUOp_ADD   4'b0000
`define ALUOp_SUBU  4'b0011
`define ALUOp_AND   4'b0100
`define ALUOp_OR    4'b0101
`define ALUOp_SLT   4'b1010
`define ALUOp_LU 4'b1111 
`define ALUOp_ADDI 6'b001000
`define ALUOp_ADDIU 6'b001001
`define ALUOp_ANDI 6'b001100
`define ALUOp_ORI 6'b001101
`define ALUOp_LUI 6'b001111
`define ALUOp_SW 6'b101011
`define ALUOp_LW 6'b100011

`define PC_J 2'b00
`define PC_4 2'b01
`define PC_JR 2'b10
`define PC_BEQ 2'b11

`define NUM_WRITE_RT 2'b00 
`define NUM_WRITE_RD 2'b01
`define NUM_WRITE_IMM 2'b10

`define ALU_GPR 1
`define ALU_IMM 0 

`define MEM_ALU 2'b00
`define MEM_MEM 2'b01
`define MEM_PC 2'b10

2.2 Be able to execute addu Single cycle of CPU

Instructions

addu The instruction format of is

Mnemonic symbol	op	rs	rt	rd	shamt	funct
addu	000000	rs	rt	rd	00000	100001

according to pc Value fetches an instruction from the instruction memory , As defined by the directive , Read from register file GPR[rs] and GPR[rt], use ALU Module implementation GPR[rs]+GPR[rt], Store results in register GPR[rd] in . Instructions are executed at the same time , adopt pc+4 Calculate the address of the next instruction npc.

The results verify that

Use mars The assembler writes mips Assembly code

Load the instruction text file into the test file , The results are as follows

The result is correct

2.3 Be able to execute R A single cycle of type instruction CPU

Instructions

Mnemonic symbol	op	rs	rt	rd	shamt	funct
addu	000000	rs	rt	rd	0	100000
subu	000000	rs	rt	rd	0	100011
add	000000	rs	rt	rd	0	100000
and	000000	rs	rt	rd	0	100100
or	000000	rs	rt	rd	0	100101
slt	000000	rs	rt	rd	0	101010

Instruction format and addu The same instruction ： The function codes are 0; The opcode determines ALU Operation type of ;ALU The two source operands of are registers GPR[rs] and GPR[rt];ALU The result is written to the register GPR[rd].

Changes that need to be made

• alu Modules need to be added or subtracted 、 And 、 or 、 Compare （<） function ;
• alu The module needs to add a selection signal aluop, Decide which type of operation to perform ;
• increase ctrl modular , Generate control signals （ At present, only aluop Signals and reg_write The signal ）.

The results verify that

Write assembly verifier , Load the program into the simulation file , The following results are obtained in the result output area

# PC=0x00003000 Aluop=0x0001
#  a=0x00000018 b=0x0000000f c=0x00000027
# PC=0x00003004 Aluop=0x0011
#  a=0x00000018 b=0x0000000f c=0x00000009
run
run
# PC=0x00003004 Aluop=0x0011
#  a=0x00000018 b=0x0000000f c=0x00000009
run
run
# PC=0x00003004 Aluop=0x0011
#  a=0x00000018 b=0x0000000f c=0x00000009
# PC=0x00003008 Aluop=0x0000
#  a=0x00000012 b=0x00000013 c=0x00000025
run
run
# PC=0x00003008 Aluop=0x0000
#  a=0x00000012 b=0x00000013 c=0x00000025
run
run
# PC=0x00003008 Aluop=0x0000
#  a=0x00000012 b=0x00000013 c=0x00000025
# PC=0x0000300c Aluop=0x0100
#  a=0x00000018 b=0x0000000f c=0x00000008
run
run
# PC=0x0000300c Aluop=0x0100
#  a=0x00000018 b=0x0000000f c=0x00000008
run
run
# PC=0x0000300c Aluop=0x0100
#  a=0x00000018 b=0x0000000f c=0x00000008
# PC=0x00003010 Aluop=0x0101
#  a=0x00000018 b=0x0000000f c=0x0000001f
run
run
# PC=0x00003010 Aluop=0x0101
#  a=0x00000018 b=0x0000000f c=0x0000001f
run
run
# PC=0x00003010 Aluop=0x0101
#  a=0x00000018 b=0x0000000f c=0x0000001f
# PC=0x00003014 Aluop=0x1010
#  a=0x00000018 b=0x0000000f c=0x00000000
run
run
# PC=0x00003014 Aluop=0x1010
#  a=0x00000018 b=0x0000000f c=0x00000000

The obtained simulation waveform is shown in Figure

2.4 add to I Type command

Instructions

Mnemonic symbol	op	rs	rt	immediate
addi	001000	rs	rt	imm
addiu	001001	rs	rt	imm
andi	001100	rs	rt	imm
ori	001101	rs	rt	imm
lui	001111	00000	rt	imm

Changes needed

• Need to add an extender , Implement immediate extension

• Need to add one alu Input source

• It is necessary to set the control signal corresponding to the command

case(op)
            `ALUOp_ADDI:
            begin 
            aluop=`ALUOp_ADD;s_b=0;s_ext=1;s_num_write=`NUM_WRITE_RT;
            reg_write=1;mem_write=0;s_data_write=`MEM_ALU;s_npc=`PC_4;
            end
            `ALUOp_ADDIU:
            begin 
            aluop=`ALUOp_ADDU;s_b=0;s_ext=1;s_num_write=`NUM_WRITE_RT;
            reg_write=1;mem_write=0;s_data_write=`MEM_ALU;s_npc=`PC_4;
            end
            `ALUOp_ANDI:
            begin 
            aluop=`ALUOp_AND;s_b=0;s_ext=0;s_num_write=`NUM_WRITE_RT;
            reg_write=1;mem_write=0;s_data_write=`MEM_ALU;s_npc=`PC_4;
            end
            `ALUOp_ORI:
            begin 
            aluop=`ALUOp_OR;s_b=0;s_ext=0;s_num_write=`NUM_WRITE_RT;
            reg_write=1;mem_write=0;s_data_write=`MEM_ALU;s_npc=`PC_4;
            end
            `ALUOp_LUI:
            begin
            aluop=`ALUOp_LU;s_b=0;s_ext=0;s_num_write=`NUM_WRITE_RT;
            reg_write=1;mem_write=0;s_data_write=`MEM_ALU;s_npc=`PC_4;
            end

The results verify that

The assembler is as follows

addi $t1 $t2,1
addiu $t2 $t3,1
andi $t3 $t4,100
ori $t4,$t5,1
lui $t6,1

The operation results are as follows

2.5 add to mem Type command

Instructions

Mnemonic symbol	op	rs	rt	imm
sw	101011	rs	rt	imm
lw	100011	rs	rt	imm

Changes needed

• increase dm modular , And connect it into the design
• Add data selector
• Register heap adds a write source

The results verify that

Instructions for

sw $t1,0($t2)
lw $t3,0($t3)

The simulation waveform is

2.5 add to J Type command

Instructions

J Type command

Mnemonic symbol	31-26	25-21	20-16	15-11	10-6	5-0
beq	000100	rs	rt	offset
j	000010	instr_index
jal	000011	instr_index
jr	000000	rs	00000	00000	00000	001000

The changes that need to be made are

• Add one more npc modular , common 4 Multiple input sources
  • pc+4
  • gpr Modules get
  • 16 Immediately
  • 26 Immediately
• The controller adds the corresponding signal
• alu increase zero sign , be used for beq Judge
• Write data selector increases pc+4

The results verify that

The experiment teacher gave the test code fibonacci.asm

.text

    addi     $t5,$t5,40     #  $t5 = 20
    
    li      $t2, 1                  # $t2 = 1 
    sw      $t2, 0($t0)             # store F[0] with 1
    sw      $t2, 4($t0)             # store F[1] with 1
    sw      $t2, 8($t0)             # store F[2] with 1
    ori     $t6, $zero, 3           # $t6 = 3
    subu    $t1, $t5, $t6           # the number of loop is (size-3)
    ori     $t7, $zero, 1           # the lastest loop $t7 = 1

    addi    $t0, $t0, 12             # point to F[3]
    
Loop:
    slt     $t4, $t1, $t7           # $t4 = ($t1 < 1) ? 1 : 0
    beq	    $t4, $t7, Loop_End      # repeat if not finished yet
    lw      $a0, -12($t0)           # $a0 = F[n-3]
    lw      $a1, -8($t0)            # $a0 = F[n-2]
    lw      $a2, -4($t0)            # $a1 = F[n-1]
    jal     fibonacci               # F[n] = fibonacci( F[n-3], F[n-2], F[n-1] )
    sw      $v0, 0($t0)             # store F[n]
    addi    $t0, $t0, 4             # $t0 point to next element
    addi    $t1, $t1, -1            # loop counter decreased by 1
	j       Loop
	
Loop_End:    
    lui     $t6, 0xABCD             # $t6 = 0xABCD0000
    sw      $t6, 0($t0)             # *$t0 = $t6
Loop_Forever:
    j       Loop_Forever            # loop forever

fibonacci :
    addu    $v0, $a0, $a1	# $v0 = x + y
    addu    $v0, $v0, $a2	# $v0 = x + y
    jr      $ra             # return

Several key points lie in several jump instructions

The results verify that

The result is pc by 00003054, And keep cycling loop forever

In memory , give the result as follows

3. Summary of the experiment

experiment tips

Some tips learned by myself , If life deceives you , Then you might as well debug bug~

Write it yourself tb

Write it yourself tb file , Run locally first , Of course, if it passes directly , There's no need to write

Like this I wrote

`timescale 1ns/1ns
module tb_s_cycle_cpu();


reg clock,reset;

s_cycle_cpu S_CYCLE_CPU(
    .clock(clock),
    .reset(reset)
);

integer i;
initial begin 
    $readmemh("code_J.txt",S_CYCLE_CPU.IM.ins_memory);// The resulting sink code 
$monitor("PC=0x%8X",S_CYCLE_CPU.PC.pc);
clock=1;
reset=0;
for(i=0;i<=31;i=i+1)
S_CYCLE_CPU.GPR.gp_registers[i]=0;

//S_CYCLE_CPU.GPR.gp_registers[31]=32'h0000_303c;

#20
reset=1; 
end
always
begin
fork
#50 clock=~clock;
#200 $monitor("PC=0x%8X Aluop=0x%4b\n a=0x%8h b=0x%8h c=0x%8h",
S_CYCLE_CPU.PC.pc,S_CYCLE_CPU.ALU.aluop,S_CYCLE_CPU.ALU.a,S_CYCLE_CPU.ALU.b,S_CYCLE_CPU.ALU.c);
join
end
endmodule

You can give the signal value to display perhaps monitor come out （ Of course, there is no need , It is better to look directly at the signal waveform ）

Write simulation script

I wrote one sim.do

quit -sim; # Exit the previous simulation 
.main    clear; # Clear the screen 


vsim -gui -novopt work.tb_s_cycle_cpu; # Simulation without parameters 
add wave sim:/tb_s_cycle_cpu/S_CYCLE_CPU/*; # Add all signals 

add wave -position insertpoint -radix hex -color white \
sim:/tb_s_cycle_cpu/S_CYCLE_CPU/GPR/gp_registers
# Set the position and color of the added signal 
add wave -position insertpoint  -radix hex -color yellow\
sim:/tb_s_cycle_cpu/S_CYCLE_CPU/DM/data_memory

virtual type {
	{2'b00 PC_J}
	{2'b01 PC_4}
	{2'b10 PC_JR}
	{2'b11 PC_BEQ}
} PC_STYLE; # Set enumeration , Add signal character name 

virtual function {(PC_STYLE)/tb_s_cycle_cpu/S_CYCLE_CPU/s_npc} s_npc_style; # Generate a new signal 
add wave -binary -color pink /tb_s_cycle_cpu/S_CYCLE_CPU/s_npc_style

run 200us; # Run for a certain time 

So that you don't have to add wave ah , Change the format , You can also set the enumeration value string to mark the signal , You can also set the signals in various colors , Beauty is not true

Problems encountered in the experiment and their solutions

problem 1

The front ones are all quite smooth , It's the last one j Type command , Compare twists and turns

Submit it , Always prompt that the running time is too long , Later, I asked my teachers and classmates , Found the problem

The original problem lies in this instruction

After this instruction is executed ,pc Will jump to

But my jump to 00000000, Analysis instructions

take gpr[31] The value of is put into pc, Found me gpr[31] The value of is 0！

So in gpr.v Just modify it in the

problem 2

This is a classmate's question

He's been running , Can't stop

This is the termination condition beq The problem of

I gave a way

Anyway, my experience is , Find out which instruction is wrong first , Go back and see if the control signal is complete , Next, let's see if the result of the operation unit is correct , There are so many basic problems

The two experiments lasted about two days

Reference material

An example

Compress

String

verilog Script emulation

Another simulation script