Zcu102 PL end running water lamp

Detailed operation steps , Please refer to ：https://blog.csdn.net/botao_li/article/details/85257566

This article only adds some notes .

#IO constraint 
set_property PACKAGE_PIN AL12 [get_ports {leds[7]}]
set_property PACKAGE_PIN AH14 [get_ports {leds[6]}]
set_property PACKAGE_PIN AH13 [get_ports {leds[5]}]
set_property PACKAGE_PIN AJ15 [get_ports {leds[4]}]
set_property PACKAGE_PIN AJ14 [get_ports {leds[3]}]
set_property PACKAGE_PIN AE13 [get_ports {leds[2]}]
set_property PACKAGE_PIN AF13 [get_ports {leds[1]}]
set_property PACKAGE_PIN AG14 [get_ports {leds[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {leds[0]}]

set_property PACKAGE_PIN G21 [get_ports clk_p]
#set_property PACKAGE_PIN F21 [get_ports clk_n]
set_property IOSTANDARD LVDS_25 [get_ports clk_p]
set_property IOSTANDARD LVDS_25 [get_ports clk_n]

# Clock period constraint 
#“create_clock” Is the name of the command , It will create a clock ;
#  The subsequent “-name clk_125_in”、“-period 8”、“[get_ports clk_p ]” Are all parameters of the command ,
#  The names of the created clocks are “clk_125_in”、 The clock period is  8ns、 The clock source is  clk_p  port 
# -period 8.000  -waveform {0.000 4.000} ： Represents the clock cycle 8ns, The rising edge is at 0ns The location of , The falling edge is at 4ns The location of 
create_clock -period 8.000 -name clk_125_in -waveform {0.000 4.000} [get_ports clk_p]

Corresponding Verilog The code is as follows ： 

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2020/01/06 19:17:04
// Design Name: 
// Module Name: pl_top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module pl_top(
    input clk_p,
    input clk_n,
    output [7:0] leds
    );
    
    wire clk;//125MHz Working clock 
    
    // Realize the conversion of differential clock to single terminal with primitive 
    IBUFDS
    #(
    .IOSTANDARD("DEFAULT")//DEFAULT Default to all cases 
    )
    IBUFDS_inst
    (
    .O(clk),// Output 
    .I(clk_p),//P End input 
    .IB(clk_n)//N End input 
    );
    
    // Define the output register 
    reg [7:0] leds = 8'b0000_0001;
    
    // Counter , timing 1 second , Counting range 0~27'd125_000_000-1
    reg [26:0] cnt = 27'd0;
    
    always @(posedge clk) begin
        case (cnt)
            27'd124_999_999: begin
                cnt <= 27'd0;// Count reset 
                leds <= {leds[6:0], leds[7]};// Cyclic shift 
            end
            
            default: begin
                cnt <= cnt+27'd1;// Count 
                leds <= leds;// keep 
            end
        endcase
    end

endmodule