SDRAM Controller Design (two design methods of digital controller)

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FPGA And SDRAM controller Design （ Two ）： Refresh

This time, we need to solve the refresh problem left last time , stay 100us After that, you need to refresh twice before setting the mode register . The star SDRAM The chip needs every 64ms Yes 8192 That's ok （ Column address 10- position , Line address 13 position ） Each storage capacitor of is refreshed once , Because not refreshing the charging will leak the current and cause the loss of stored information . The refresh time of each line is 64/8192 ≈ 7810ns, Note that the refresh is in behavioral units , There is a counter inside the chip , This counter is not directly driven by the clock , It is AUTO PRECHARGE drive , Every time atuoprecharge Command this counter to add 1, We can't see it or set it directly , This counter is initialized as soon as it is powered on, which we don't need to care about , What we have to do is 7810ns Just perform a refresh operation . The read and write are performed within two refresh intervals , This will be discussed in the next section .

The design idea of the refresh module is : The refresh command state machine and a counter generated by the refresh flag , On this basis, a master state machine should be added , That is, a module that controls when to power on and refresh read / write .

Refresh the state transition graph ：

Refresh state machine design

`include	"head.v"
module ref_fsm(
		ref_done,ref_en,clk,ref_bus,soft_rst_n
);// Refresh state machine 
		input			clk;
		input			ref_en;
		input			soft_rst_n;
		output	reg		ref_done;
		output	[19:0]	ref_bus;
		
		reg		[12:0]	ref_a;
		reg		[1:0]	ref_ba;
		reg		[3:0]	ref_cmd;
		reg				ref_cke;
		
		assign	ref_bus = {ref_cmd,ref_a,ref_ba,ref_cke};
		
		reg		[14:0]	cnt;
		reg		[1:0]	state;
		localparam	s0 = 2'b00;
		localparam	s1 = 2'b01;
		localparam	s2 = 2'b10;
		
		
	always @(posedge clk)
		begin
			if(soft_rst_n == 1'b0)
				begin
					ref_done <= 1'b0;
					ref_ba <= 'd0;
					ref_cmd <= `NOP;
					ref_cke <= 1'b0;
					cnt <= 'd0;
					state <= s0;
				end
			else
				case(state)
					s0 : if(ref_en == 1'b0)
							begin
								ref_done <= 1'b0;
								state <= s0;
								
							end
						 else
						 	begin
						 		ref_cmd <= `PRE;
						 		ref_a[10] <= 1'b1;
						 		ref_done <= 1'b0;
						 		state <= s1;
						 		ref_cke <= 1'b1;//add
						 	end
					s1 : if(cnt < `tRP - 1)
							begin
								cnt	<= cnt + 1'b1;
								ref_cmd <= `NOP;
								state <= s1;
							end
						 else
						 	begin
						 		cnt	 <= 'd0;
						 		ref_cmd <= `REF;
						 		state <= s2;
						 	end
					s2 : if(cnt	< `tRFC - 1)
							begin
								cnt <= cnt + 1'b1;
								ref_cmd <= `NOP;
								state <= s2;	
							end
						 else
						 	begin
						 		cnt	<= 'd0;
						 		ref_done <= 1'b1;
						 		state <= s0;
						 	end
				endcase
		end
endmodule

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Timing module design

`include	"head.v"

module ref_time(
	clk,soft_rst_n,rt_en,rt_flag
);// Refresh timer 
	input		clk;
	input		rt_en;
	input		soft_rst_n;
	output	reg	rt_flag;
	
	reg		[9:0]	cnt;

always @(posedge clk)begin
	if(soft_rst_n == 1'b0)
		begin
			cnt <= 'd0;
			rt_flag <= 1'b0;
		end
	else if(rt_en == 1'b1 )
			if(cnt < 780)
			begin
				cnt <= cnt + 1'b1;
				rt_flag <= 1'b0;
			end
			else begin
				cnt	 <= 'd0;
				rt_flag <= 1'b1;	
			end
		
end
endmodule

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