Verilog implementation of key dithering elimination

Press the key to shake off

When the key is pressed , Due to the limitations of mechanical switches , The corresponding level will not stabilize immediately , Instead, jitter will occur for a period of time . In order to correctly identify the key information , We have to deal with the key shaking .

Code implementation

Beat the input with two registers , When the values of these two registers are different （ shake ）, Reset the counter . otherwise , The counter is added every cycle 1, When the value of the counter reaches a given value , If the value of the register is valid , It means that the key has been pressed .
If the key is pressed, the value is 1, The code is as follows ：

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2022/07/22 16:43:50
// Design Name: 
// Module Name: bit_count
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module debounce(
input logic clk,
input logic rst,
input logic key_in,
output logic key_flag);

parameter CNT=1000;
logic key_d1;
logic key_d2;
logic [31:0] cnt;
//key_d2,1
[email protected](posedge clk,posedge rst)
if(rst)
   {
    key_d2,key_d1}<=2'b00;
else
   {
    key_d2,key_d1}<={
    key_d1,key_in};
//cnt
[email protected](posedge clk,posedge rst)
if(rst)
   cnt<=0;
else if(key_d1^key_d2)              // Still shaking 
   cnt<=0;
else if(cnt==CNT)
   cnt<=cnt;
else
   cnt<=cnt+1;
//key_flag
[email protected](posedge clk,posedge rst)
if(rst)
   key_flag<=0;
else if(cnt==CNT-1&&key_d2==1'b1)                 // It lasts long enough and is pressed 
   key_flag<=1;
else
   key_flag<=0;
endmodule

Test code

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2022/07/23 21:03:12
// Design Name: 
// Module Name: key_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module key_tb(

    );
reg clk;
reg rst;
reg key_in;
wire key_flag;
//clk
initial
begin
   clk=0;
   forever
      #5 clk=~clk;
end
//rst
initial
begin
   rst=1;
   #100
   rst=0;
end
//key_in
initial
begin
   key_in=0;
   wait(rst==1'b0);
   @(posedge clk);
   //
   key_in<=1;
   @(posedge clk);
   repeat(100)
   begin
       key_in<=$random;
	   @(posedge clk);
   end
   //
   key_in<=1;
   repeat(1000)
      @(posedge clk);
   //
   key_in<=0;
   repeat(100)
   begin
      key_in<=$random;
	  @(posedge clk);
   end
   @(posedge clk);
   key_in<=0;
end


//inst
debounce U(
.*
/* input logic clk, input logic rst, input logic key_in, output logic key_flag */
);

endmodule

Simulation results