Risc-v instruction set explanation (4) R-type integer register register instruction

1. R-Type Integer register - Register instructions

Above, RISC-V Instruction set explanation （3）I-Type Shift instruction and U-type Instruction introduces the integer register - Immediate instruction , This article begins with integer registers - Explanation of register instruction .

RV32I Several arithmetics are defined R-type operation . All operations will rs1 and rs2 Registers are read as source operands , And write the result to the register rd, Be careful R-type The instruction has no immediate , Only registers rs1,rs2 and rd.

funct7 and funct3 Field select the operation type , Pictured 1 Shown .

R-type Altogether 10 Orders ,opcode The name is OP, The value is 011_0011( be-all R-type The directive opcode All the same ).

chart 1 Integer register - Register instruction machine encoding format [1]

1.1. ADD

ADD Command and RISC-V Instruction set explanation （2）I-Type Integer register - Mentioned in the immediate instruction ADDI Instructions operate on a similar principle , The only difference is that it used to be 12 Position of bit immediate , Split into 7 Bit funct7 and 5 Bit rs2.

ADD The command format is ADD rd,rs1,rs2.x[rd] = x[rs1] + x[rs2]

Pictured 2 Shown ,ADD The directive funct7 by 000_0000,funct3 by 000. The instruction is to rs1 + rs2 Write the result of rd in . Be careful ： Not located by machine code bit 15-19 and bit 20-24 Add up , Instead, the values of the registers corresponding to the index numbers are added .

And ADDI similar , The overflow part is ignored ( Overflow processing can be implemented by software , Here is how to handle ), Will only be low XLEN Bit write rd.

An example of additive overflow is , Two 8 Bit binary signed numbers are added ,0100_0000（64） + 0111_0000（112） = 1011_0000(-80), The result was clearly wrong .

Instruction example ：

ADD x14,x12,x13

take x12 and x13 Add the numbers in the register , And put the results in the x14 In the register .

OP-IMM by 011_0011

funct3 by 000

funct7 by 7’b000_0000

rs2 by 5’b0_1101

rs1 by 5’b0_1100

rd by 5’b0_1110

therefore ADD x14,x12,x13  The corresponding machine code is 0000000_01101_01100_000_01110_0110011, Corresponding 16 Into the system for 32’h00d6_0733

chart 2 ADD Machine code format [2]

1.2. SLT

Again ,SLT And SLTI similar ,SLT The command format is SLT rd,rs1,rs2.x[rd] = x[rs1] <  x[rs2]

Pictured 3 Shown ,SLT The directive funct7 by 000_0000,funct3 by 010.rs1 and rs2 Compare as a signed number , If rs1 < rs2, rd Set up 1, Otherwise, set 0.

Instruction example ：

SLT x14,x12,x13

take x12 and x13 Numbers in registers are compared as signed numbers , If x12 The number in the register is less than x13 Number in register , take x14 The number in the register is set to 1, Otherwise, set to 0.

chart 3 SLT Machine code format [2]

1.3. SLTU

SLTU The instruction format of is SLTU rd,rs1,rs2.x[rd] = x[rs1] < x[rs2]

Pictured 4 Shown ,SLTU The directive funct7 by 000_0000,funct3 by 011. Unsigned comparison rs1 and rs2, If rs1 < rs2,rd Set up 1, Otherwise, set 0.

Be careful , stay SLTU rd,x0,rs2 If rs2 It's not equal to 0, be rd Be set to 1, otherwise , take rd Set as 0. The corresponding pseudo instruction is SNEZ rd,rs2

Instruction example ：

SLTU x14,x12,x13

take x12 and x13 Numbers in registers are compared as unsigned numbers , If x12 The number in the register is less than x13 Number in register , take x14 The register is set to 1, Otherwise, set to 0.

chart 4 SLTU Machine code format [2]

1.4. AND

AND The instruction format of is AND rd,rs1,rs2.x[rd] = x[rs1] & x[rs2]

Pictured 5 Shown ,AND Instructive funct7 by 000_0000,funct3 by 111. The directive will rs1 & rs2 Write the result of rd in ,“&” Express rs1 And rs2 Bit by bit facies .

Instruction example ：

AND x14,x12,x13

take x12 and x13 The number in the register is written to the result of bitwise AND x14 register .

chart 5 AND Machine code format [2]

1.5. OR

OR The instruction format of is OR rd,rs1,rs2.x[rd] = x[rs1] | x[rs2]

Pictured 6 Shown ,OR The directive funct7 by 000_0000,funct3 by 110. The directive will rs1 | rs2 Write the result of rd in ,“|” Express rs1 And rs2 Phase by phase or .

Instruction example ：

OR x14,x12,x13

take x12 and x13 The number in the register is written to the result of bit or x14 register .

chart 6 OR Machine code format [2]

1.6. XOR

XOR The instruction format of is XOR rd,rs1,rs2.x[rd] = x[rs1] ^ x[rs2]

1.7. SLL

SLL(shift left logical, Logic shift left ) The instruction format of is SLL rd,rs1,rs2.x[rd] = x[rs1] ≪ x[rs2]

1.8. SRL

SRL(shift right logical, Logical shift right ) The instruction format of is SRL rd,rs1,rs2.x[rd] = x[rs1] ≫ x[rs2]

1.9. SRA

SRA(shift right arithmetic, Arithmetic shift right ) The instruction format of is SRA rd,rs1,rs2.x[rd] = x[rs1] ≫ x[rs2]

1.10. SUB

SUB The instruction format of is SUB rd,rs1,rs2.x[rd] = x[rs1] − x[rs2]

remarks ： About after 5 A complete example of , Please search the search engine “IC The knowledge base ” see .