[mit 6.s081] LEC 9: interrupts notes

Lec 9: Interrupts

• Ref: https://github.com/huihongxiao/MIT6.S081/tree/master/lec09-interrupts
• Preparation: xv6 book Chapter 5

summary

Interrupt scenario : Hardware needs the attention of the operating system , If the network card receives a packet , The user presses the button
Interrupts and system calls , trap The mechanism is similar .

• The difference between interrupt and system call
  • asynchronous (asynchronous): When hardware generation is interrupted , Interrupt handler Interrupt handler and CPU It has nothing to do with the process currently running on ; The system call still calls the context of the process after entering the kernel Context Run in
  • Concurrent (concurrency): CPU And the device that generates the interrupt run in parallel , Equipment and CPU There is real parallelism between
  • Device programming (program device): Focus on external equipment

Interrupt related hardware

All devices are connected to the processor , Processor passes PLIC(Platform Level Interrupt Control) Handling interrupts .
PLIC Will route the terminal to a CPU The core of , If all CPU The core is dealing with interrupts , PLIC The interrupt will be kept until it is available CPU. PLIC You need to save some internal data to track the interrupted state .

• Interrupt processing flow :
  • Indicates that there is currently an interrupt , Waiting for one CPU The core claims to own it , such PLIC You won't send interrupts to other cores
  • CPU Handling interrupts , After processing, we will notify PLIC
  • PLIC The message of this interrupt will be cleared

Device drivers

drive : Code for managing devices , Drivers are in the kernel .
The drive is generally divided into two parts ( Not an address space ): The bottom part (bottom part) And the top part (top part).

• The bottom part : Usually interrupt handlers . CPU When you receive an interrupt, you will call the interrupt handler here . Interrupt handlers do not run in the context of a particular process , Just deal with interrupts
• Top section : User process , Or the interface called by the rest of the kernel . about UART, yes read/write Interface .
  Usually , There will be some queues in the driver ( buffer ). The code at the top and the interrupt handler at the bottom can read and write to the queue . The queue decouples the top and bottom parts of the drive , Operating equipment and CPU Run other code in parallel on .
  

Interrupt register

• SIE(Supervisor Interrupt Enable) register : Among them is 1 The bit (E) Special handling of peripheral interrupts , 1 A bit (S) Handling software interrupts , 1 A bit (T) Processing timer interrupt .
• SSTATUS(Supervisor Status) register . Yes 1 Bit control interrupt switch . Every CPU There are opposites SIE and SSTATUS register .
• SIP(Supervisor Interrupt Pending) register : In the event of an interruption , The processor knows the type of current interrupt according to this register
• SCAUSE register : The reason for the interruption
• STVEC register : Save the interrupt program address

Interrupt the process

• Premise : CPU Core set SIE External interrupt bit of register (E)

1. Hardware clear SIE Bits of register , Prevent any other interrupts from interrupting CPU
2. SEPC Register records the current program counter
3. Save the current mode ( user / kernel )
4. Set to kernel mode (supervisor mode)
5. Set the value of the program counter to STVEC Register value
   

Interruption and concurrency

• Aspects of interrupt concurrency :
  • Equipment and CPU It runs in parallel . The behavior here is not the producer / Consumers in parallel
  • Interrupt will stop the currently running program .
  • Top of drive (top) And the bottom (bottom) Part of it runs in parallel . Can run in parallel in different CPU, Parallel through lock management .
    
• producer / Consumers in parallel
  • The circular queue
  • Team space : Read pointer == The write pointer
  • The team is full : The write pointer +1 == Read pointer . When the team is full, the producer will sleep .
    

Interrupted development

In the past : Interrupts are handled quickly , The hardware can be designed simply
Now? : Interrupt processing slows , It takes a lot of steps , The equipment needs more work , To lessen CPU Deal with the burden

For fast devices ( High performance equipment , Under normal circumstances CPU Processing requires a lot of interrupts , exceed CPU Its own processing ability ) The processing method is polling (polling): CPU Keep polling (spin) Device until there is data , But it will waste CPU cycle (cycles).
For slow devices , There's no need to poll , But when there is no data CPU Switch to other devices .