Static timing analysis (STA) in ic/fpga design

The concept of static timing analysis

Static time series analysis （Static Timing Analysis, STA）, Or static timing verification , In Electronic Engineering , Calculate the timing of digital circuits 、 Expected workflow , This process does not need to be simulated by inputting incentives . It is IC/FPGA A crucial part of design , It is also a common point in written examination interview

Setup time and hold time

As shown in the figure , Set up time $T_{setup}$ It means before the rising edge of the clock , The minimum time that the data must remain stable , In order to ensure that the data is correctly used , And hold time $T_{hold}$ It means after the rising edge of the clock , The data still needs to remain stable for a minimum time , So that the data can be transmitted correctly , One of the two is not satisfied , The circuit may not work properly .

STA Classic example

As shown in the figure ,Comb Represents combinatorial logic ,Clock Skew Indicates clock offset , Assume that the two D Triggers are triggered at the rising edge .$T_{cq}$ For registers clock End to Q End delay ,$T_{comb}$ Is the delay of combinatorial logic ,$T_{su}$ and $T_{hd}$ Respectively, the establishment time and holding time of the register ,$T_{skew}$ Is the clock offset ,$T_{clk}$ Is the clock period , It is required to write down the constraints that the establishment time and holding time should meet .

As shown in the figure , With CLK1 The first rising edge of is the origin , be Q1 stay $T_{cq}+T_{comb}$ Stable , and CLK2 The second rising edge of is $T_{clk}+T_{skew}$ arrive , Defined by the establishment time , To make the circuit work properly , Then there are
$$T_{cq}+T_{comb}+T_{su}\le T_{clk}+T_{skew}\text{\hspace{1em}(1)}$$
According to the above formula , It is not difficult to find that the maximum clock frequency is
$$f_{max}=\frac{1}{T_{cq}+T_{comb}+T_{su}-T_{skew}}$$
Then consider holding time , This time with the second CLK1 The rising edge is the origin , be Q1 stay $T_{cq}+T_{comb}$ Time changes , and CLK2 The rising edge of $T_{skew}$ achieve , According to the definition of holding time , To make the circuit work properly , Then there are
$$T_{cq}+T_{comb}-T_{skew}\ge T_{hd}\text{\hspace{1em}(2)}$$
Of course , If wiring delay is considered , Then there is the following formula :