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[stm32] internal independent watchdog iwdg
2022-07-24 12:48:00 【weixin_ forty-three million seven hundred and seventy-one thous】
The watchdog should be familiar to everyone ,STM32 There are two kinds of independent watchdog and window watchdog inside ; The independent watchdog depends on the internal crystal LSI Work on , The window watchdog depends on the system clock ;
The role of the watchdog , Prevent the program from running and cannot realize self reset ; If there is no watchdog , The program is down , May need to go to MCU Power on , Power on again to continue working , thus it can be seen , The watchdog plays an important role in a system .
Easy to operate , Reduce the reload value to 0 Before , Reload the register value , Let the register value always be greater than 0;
1、 Introduction to working principle
When passing through the key register (IWDG_KR) Write the value 0xCCCC When starting the independent watchdog , The counter starts from reset value 0xFFF Decrement count . When the counter reaches the final value (0x000) It will generate a reset signal (IWDG Reset ). Any time will keyword 0xAAAA writes IWWDG_KR In the register ,IWDG_RLR The value of will be overloaded into the meter The counter , So as to avoid the reset of watchdog .
2、 Dog feeding cycle range

3、 Design thinking , Why online debugging MCU when ,MCU Not reset ?
IWDG: Overload register (IWDG_RLR) The reload value is not reduced to 0;
Extend a topic : External watchdog , How to ensure no reset during debugging ?
have access to Jlink hold RST The level of is stable , Don't let the watchdog chip pull down RST level ;
4、IWDG Common problems caused
Inside FLASH The erasure cycle is greater than IWDG Dog feeding cycle ;
Because inside FLASH In operation , Is to use the bus to operate registers , The bus is in the occupied state , At the completion of FLASH Before command operation , Can't do anything , As a result, the dog feeding signal cannot be sent , Dog feeding timeout ,MCU Reset ; I suffered this loss in those years , Mainly aimed at 128KB For sector block erasure , Probably need 800ms;IWDG The cycle is best set at 1S above ;
External watchdog 1.6S cycle , There is no such problem .
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