Verilog data type

Verilog data type

Verilog Most commonly used 2 One data type is the wire network （wire） And registers （reg）, The other types can be understood as the extension or auxiliary of these two data types .

Wire network （wire）

wire Type indicates the physical connection between hardware units , The device output connected by it is continuously driven . If no drive element is connected to the wire Type variable , The default value is generally "Z". Examples are as follows ：

example

wire   interrupt ;
wire   flag1, flag2 ;
wire   gnd = 1'b0 ;  

Network type and other data types , Include wand,wor,wri,triand,trior,trireg etc. . These data types are not used very often , No introduction here .

register （reg）

register （reg） Used to represent a storage unit , It will keep the original value of the data , Until it is rewritten . Examples of statements are as follows ：

example

reg    clk_temp;
reg    flag1, flag2 ;

For example, in always In block , Registers may be integrated into edge triggers , In combinatorial logic, it may be integrated into wire Type variable . The register does not require a drive source , You don't need a clock signal . In simulation , The value of the register can be rewritten by assignment at any time . for example ：

example

reg rstn ;
initial begin
    rstn = 1'b0 ;
    #100 ;
    rstn = 1'b1 ;
end

vector

When the bit width is greater than 1 when ,wire or reg Can be declared as a vector . for example ：

example

reg [3:0]      counter ;    // Statement 4bit Bit wide register counter
wire [32-1:0]  gpio_data;   // Statement 32bit Bit width linetype variable gpio_data
wire [8:2]     addr ;       // Statement 7bit Bit width linetype variable addr, The bit width range is 8:2
reg [0:31]     data ;       // Statement 32bit Bit wide register variable data, The most significant bit is 0

For the above vector , We can specify one or several adjacent bits , Used as other logic . for example ：

example

wire [9:0]     data_low = data[0:9] ;
addr_temp[3:2] = addr[8:7] + 1'b1 ;

Verilog Support variable vector field selection , for example ：

example

reg [31:0]     data1 ;
reg [7:0]      byte1 [3:0];
integer j ;
[email protected]* begin
    for (j=0; j<=3;j=j+1) begin
        byte1[j] = data1[(j+1)*8-1 : j*8];
        // hold data1[7:0]…data1[31:24] Assign values to byte1[0][7:0]…byte[3][7:0]
    end
end

Verillog It also supports specifying bit Vector field selection access with fixed bit width after bit .

• [bit+: width] : From start bit Bits begin to increment , The seat width is width.
• [bit-: width] : From start bit Bits begin to decrease , The seat width is width.

example

// below 2 Each assignment is equivalent
A = data1[31-: 8] ;
A = data1[31:24] ;

// below 2 Each assignment is equivalent
B = data1[0+ : 8] ;
B = data1[0:7] ;

When recombining signals into new vectors , You need braces . for example ：

example

wire [31:0]    temp1, temp2 ;
assign temp1 = {byte1[0][7:0], data1[31:8]};  // Data splicing
assign temp2 = {32{1'b0}};  // assignment 32 The number of bits 0  

Integers , The set of real Numbers , Time register variables

Integers , The set of real Numbers , Data types such as time actually belong to register types .

Integers （integer）

Integer types use keywords integer To declare . Do not specify the bit width when declaring , The bit width is related to the compiler , It's usually 32 bit.reg Type variable is an unsigned number , and integer Type variable is a signed number . for example ：

example

reg [31:0]      data1 ;
reg [3:0]       byte1 [7:0]; // An array variable , Follow up
integer j ;  // Integer variables , Used to assist in the generation of digital circuits
[email protected]* begin
    for (j=0; j<=3;j=j+1) begin
        byte1[j] = data1[(j+1)*8-1 : j*8];
        // hold data1[7:0]…data1[31:24] Assign values to byte1[0][7:0]…byte[3][7:0]
        end
end

In this case ,integer The signal j As an auxiliary signal , take data1 The data of is assigned to the array in turn byte1. After synthesis, there is no in the actual circuit j This signal ,j It only helps to generate the corresponding hardware circuit .

The set of real Numbers （real）

Keywords for real numbers real To declare , Can be expressed in decimal or scientific notation . A real number declaration cannot have a range , The default value is 0. If you assign a real number to an integer , Only the integer part of the real number is assigned to the integer . for example ：

example

real        data1 ;
integer     temp ;
initial begin
    data1 = 2e3 ;
    data1 = 3.75 ;
end
 
initial begin
    temp = data1 ; //temp The size of the value is 3
end

Time （time）

Verilog Use a special time register time Type variable , Save the simulation time . Its width is generally 64 bit, By calling system functions $time Get the current simulation time . for example ：

example

time       current_time ;
initial begin
       #100 ;
       current_time = $time ; //current_time The size is 100
end

Array

stay Verilog It is allowed to declare reg, wire, integer, time, real And an array of vector types .

There is no limit to the dimension of an array . The wire network array can also be used to connect the ports of the instance module . Each element in the array can be used as a scalar or vector , Use... In the same way , Form like ：< Array name >[< Subscript >]. For multidimensional arrays , The user needs to specify the index of each dimension . for example ：

example

integer          flag [7:0] ; //8 An array of integers
reg  [3:0]       counter [3:0] ; // from 4 individual 4bit Array of counters
wire [7:0]       addr_bus [3:0] ; // from 4 individual 8bit wire An array of type variables
wire             data_bit[7:0][5:0] ; // Statement 1bit wire A two-dimensional array of type variables
reg [31:0]       data_4d[11:0][3:0][3:0][255:0] ; // Statement 4 Dimensional 32bit Data variable array

The following shows the assignment operation to the array elements ：

example

flag [1]   = 32'd0 ; // take flag The second element in the array is assigned to 32bit Of 0 value
counter[3] = 4'hF ;  // Will array counter pass the civil examinations 4 The value of each element is assigned to 4bit Hexadecimal number F, Equivalent to counter[3][3:0] = 4'hF, The width can be omitted ;
assign addr_bus[0]        = 8'b0 ; // Will array addr_bus The value of the first element in the is assigned to 0
assign data_bit[0][1]     = 1'b1;  // Will array data_bit Of the 1 Xing di 2 The element of the column is assigned to 1, The second access label cannot be omitted here , namely assign data_bit[0] = 1'b1; It's illegal. .
data_4d[0][0][0][0][15:0] = 15'd3 ;  // Will array data_4d The bid winning number is [0][0][0][0] Of the register unit 15~0bit The assignment is 3

Although arrays and vectors are accessed in a way similar , But don't confuse vectors with arrays . A vector is a single component , The seat width is n; The array consists of multiple components , The bit width of each element is n or 1. They differ in the definition of structure .

Memory

A memory variable is an array of registers , Can be used to describe RAM or ROM act . for example ：

example

reg               membit[0:255] ;  //256bit Of 1bit Memory
reg  [7:0]        mem[0:1023] ;    //1Kbyte Memory , A wide 8bit
mem[511] = 8'b0 ;                  // Lingdi 512 individual 8bit The storage unit value of is 0

Parameters

Parameters are used to represent constants , With keywords parameter Statement , Can only assign once . for example ：

example

parameter      data_width = 10'd32 ;
parameter      i=1, j=2, k=3 ;
parameter      mem_size = data_width * 10 ;

however , By way of instantiation , You can change the value of the parameter in the module . This section will cover .

For local parameters localparam To declare , Its function and usage are similar to parameter identical , The difference is that its value cannot be changed . So when parameters are only called in this module , You can use localparam To illustrate .

character string

The string is saved in reg In variables of type , One byte per character （8bit）. Therefore, the width of the register variable should be large enough , To ensure no spillage .

String cannot be written in more than one line , That is, the string cannot contain carriage return . If the width of the register variable is greater than the size of the string , Then use 0 To fill the empty space on the left ; If the width of the register variable is less than the string size , The redundant data on the left of the string will be truncated . for example , To store strings "run.runoob.com", need 14*8bit The storage unit of ：

example

reg [0: 14*8-1]       str ;
initial begin
    str = "run.runoob.com";
end  

There are some special characters that have special meanings in the display string , For example, line breaks , Box drawings, etc . If you need to display these special characters in the string , You need to prefix the escape character  \ . For example, as shown in the following table ：

Escape character	Show characters
\n	Line break
\t	tabs
%%	%
\	\
\"	"
\ooo	1 To 3 individual 8 Hexadecimal numeric characters