Advanced extensible interface (Axi)

《IHI0022H_amba_axi_protocol_spec》
AMBA3.0 agreement ——AXI（Advanced eXtensible Interface） Bus Introduction
AXI_01 《AXI Bus series 》 origin

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1. Function is introduced

AMBA The most important on-chip bus in , For high performance 、 High bandwidth 、 High operating frequency 、 Low delay system , Is based on The Lord and from much Architecture and transaction transfer of .

AXI Features include ：

● Single channel system , That is, the control channel and data channel are separated from each other , Can be independently controlled and optimized . And the transmission direction of each channel is single , Reduce the delay .

● Support byte gating 、 Non aligned data access

● Only the first address is given , Can also be completed burst transmission

● Based on transmission ID Realize out of order transmission

● Allow level synchronization

2. framework

2.1. From that master sheet

Let's start with one master、 One slave How do we communicate with each other .

AXI take master And slave The control information and data information are divided into five channels for transmission , The five channels are time independent , These five channels represent ： Read control channel AR、 Read data channel R、 Write control channel AW、 Write data channel W、 Write feedback channel B

Each channel consists of several signals
AXI Channel decomposition architecture and APB、AHB Different ,APB The control information and data information are required to be time aligned ,AHB The difference between control information and data information is required 1 Clapping makes flowing water .

Here's the picture

These five channels are based on valid & ready Handshake signal realizes control information or Data information interaction

In fact, it is the write timing in the standard handshake protocol , Only when valid And ready When it is high at the same time, it is determined that the writing is successful .
here AXI Is that each channel is valid And ready At the same time, it is determined that the transmission is successful only when it is high .

passageway	handshake	remarks
Write control channel AW	Master towards Slave transmission ,valid & ready handshake
Write data channel W	Master towards Slave transmission ,valid & ready handshake	Write data strobe function . And the data can be written through FIFO cache , There is no need to wait for write feedback before initiating a new round of writing
Read control channel AR	Master towards Slave transmission ,valid & ready handshake
Read data channel R	Slave towards Master transmission ,valid & ready handshake	Contains read data , It also contains a read response indicating the completion of the read transmission
Write feedback channel B	Slave towards Master transmission ,valid & ready handshake	You need to respond to each write transaction

2.2. The Lord and from much

AXI It can also realize the structure of multi master and multi slave , Be similar to Bus Matrix

Here's the picture ,Interconnect At the same time have AXI master Interface and AXI slave Interface

In fact, the control channel bandwidth of most systems is significantly smaller than the data channel bandwidth , So for multi master and multi slave systems , adopt Shared control channel 、 Independent data channel Achieve system performance and interconnect The balance of complexity .

3. Signal description

Global signal

Signal	Source	Width(bits)	Description
ACLK	external	1
ARESTn	external	1	Low level reset

3.1. AW

Signal	Source	Width(bits)	Description
AWID	Master	AWID_WIDTH	Write business ID
AWADDR	Master	AWADDR_WIDTH	burst Write transactions first WDATA The address of
AWLEN	Master	8	Write the transaction this time WDATA Number -1
AWSIZE	Master	3	WDATA Effective in byte size
AWBURST	Master	2	burst Transfer type
AWLOCK	Master	2	The atomic nature of writing transactions
AWCACHE	Master	4	Write the requirements for running transactions in the system
AWPROT	Master	3	Write transaction protection properties ： Privilege 、 Security level 、 Access type
AWQOS	Master	4	Write the quality of service identifier of the transaction
AWREGION	Master	4	Write the area indicator of the transaction
AWUSER	Master	USER_REQ_WIDTH	Customize
AWVALID	Master	1	AWADDR It works
AWREADY	Slave	1	AWADDR Prepare to receive

Parameter	Units	Description
AWID_WIDTH	bit	AXI AW The tunnel AWID A wide
AWADDR_WIDTH	bit	AXI AW The tunnel AWADDR A wide
USER_REQ_WIDTH	bit	AXI AW The tunnel AWUSER and AR The tunnel ARUSER A wide

3.2. W

3.3. AR

3.4. R

3.5. B