SystemVerilog simulation speed increase

Dynamic simulation verification usually involves waiting for simulation results , Especially when debugging a test case . A lot of times , Engineers naturally think that the speed of simulation depends largely on the performance of the server running the simulation task , as well as EDA Capabilities of simulation tools . But in fact , Efficient verification environment and code quality are also the key factors that affect the simulation speed .

On the other hand , Increasing the speed of simulation , For chip engineers, it is “ Better to ask for yourself than for others ”. Improving server machine performance means greater capital investment , Higher performance simulation tools will not be achieved in a while . And explore more efficient validation methodologies , Building more efficient code is something you can do right now .

The main content of this article is from Cliff Cummings stay 2019 year DVCon Articles published at the conference ：Yikes! Why is My SystemVerilog Still So Slooooow. This article mainly discusses SystemVerilog The simulation speed is the same as Coding The relationship between styles , There are detailed experimental objectives in the article 、 Methods and data results are presented . This article will extract and analyze those coding styles that have a great impact on the simulation speed .

1. Use vector operations instead of single bit operation
The emulator is doing complete vector computation faster than a single bit Calculate high . According to the data of references , Under a certain simulation tool , The maximum acceleration can reach 3 More than times .
Here is a routine , Present different code implementation styles .

2. Avoid instantiating objects in loops
This technique relates to memory allocation and recycling . Inefficient memory management can lead to severe cache miss、 Stack management overhead and garbage collection overhead , Although these are all done by the operating system .
When we need a new data structure , Body structure can be used struct You don't have to class, Instantiation of classes and garbage collection are both overhead . When creating an object , Don't just come up here new, Consider whether you can reuse previously created objects .
The following routine , The application of this technique in the three mainstream simulation tools can bring simulation speed benefits , The maximum speed is increased by more than half .

3. Conditional judgment string processing
During the simulation process, printing information or reading and writing files will lead to very slow simulation speed , After all, call the computer IO It's not efficient . stay UVM There are sound report Management mechanism , Can be set according to verbosity Level to determine whether it is necessary to print information .
In addition to information printing , The format processing of strings is also very expensive . If I borrow report To determine whether it is necessary to perform string format processing , It can effectively improve the simulation speed .
The following routine , Code with conditional judgment can bring simulation speed benefits on the three mainstream simulation tools , And the income is very large , Reached 33 times ~100 times .

4. Reduce unnecessary port sampling or driving
This is another technique to reduce unnecessary operations . Know that UVM in , operation TLM analysis port It costs a lot , Because the driver behavior of the port , All the data associated with the port will be executed through the callback mechanism consumer Port action for . Understand the implementation mechanism , Actually, I have to see UVM Source code , There is no need to expand and resolve .
Besides , Some analysis port Whether to connect to other component Is dependent on the current authentication environment , If according to analysis port To determine whether to drive the port , It can reduce some unnecessary operations .
The following routine , stay monitor Of run_phase According to its analysis port Status to sample ports and broadcast to other components , It can bring a part of the benefit of simulation speed .

5. Replace inefficient random constraints with callback functions
SystemVerilog There are many ways to randomize variables and add random constraints , For details, please refer to the other two articles in the official account 《 Hidden mystery SV randomization 》《 All kinds of SystemVerilog Random constraint 》. When designing random constraints , In addition to ensuring that constraints do not conflict （ That is, the constraint has a solution ） outside , It is also necessary to avoid invalid constraint solutions .
Actually ,SV Already available pre_randomize() / post_randomize() Two callback functions that will be executed before and after the random value is solved . Using these two functions flexibly can avoid some very inefficient constraint behaviors .
The following routine , Use post_randomize Sort the random sequence , You can avoid using loops in constraints to restrict each sequence element , Thus, the simulation speed is increased by tens of times .