VCs compilation and simulation process

 VCS The build process ：

1. Processing parameters ：

When typing make compile after ,Makefile Going to call vcs This executable file , And throw a bunch of parameters to it

and vcs This executable is actually a script , A script that can handle hundreds of parameters

2. Code processing ：

Preprocessing ：  send ⽤ command ：gcc -E  -o  hello.i  hello.c

compile ：    send ⽤ command ：gcc -S  -o  hello.s  hello.i

assembly ：    send ⽤ command ：gcc  -c -o  hello.o  hello.s

Preprocessing / compile / assembly ： This vcs Will call the real compiler to compile our verilog/systemverilog Code ,

After code compilation , At this point, we get some object files 、 Dynamic library , Existential release csrc In the folder （ Notice that there is a file called Makefile）：

3. link ：

link ：   send ⽤ command ：gcc  -o    hello  hello.o

vcs Would call g++ To complete the target file 、 Links to dynamic libraries , And guidance g++ Working , It is the dolls mentioned above Makefile;

thus , Got a complete executable simv

simulation process ：

perform Executable file simv

And +UVM_TESTNAME=？ Pass in the use case name , You can simulate different use cases