ARM processor mode and register

Pattern

Different architectures define different patterns , But they are backward compatible , Here is ARM920T CPU Supported processor modes .

Schema name	Code	describe
User(USR)	10000	The user mode in which most applications run , Also called non privileged mode
FIQ	10001	FIQ Abnormal interruption
IRQ	10010	IRQ Abnormal interruption
Supervisor(SVC)	10011	The management call instruction is executed or reset When
Monitor(MON)	10110	Security extension mode , For safety purposes only
Abort(ABT)	10111	Storage access mode
Hyp(HYP)	11010	Virtualization extension
Undef(UND)	10011	When the instruction execution is not defined
System(SYS)	11111	System mode , The pattern is related to USR Mode shared register

The above modes are in addition to USR Out of mode , Other modes belong to privileged mode .

register

General registers

R0—R12 this 13 This is called a general purpose register , Generally speaking, they can be used for any purpose .

R13： Also called sp, Usually used as a stack pointer , Note that each pattern has its own R13 Register copy .

R14： Also called lr（ Connection register ）. This register serves two purposes ： One is when subroutines are called ,lr Used to save the return address ; Second, when an abnormal interrupt occurs , The specific physics of the exception pattern lr The register is set to the address to be returned by the exception mode （ This step is done automatically by hardware ）.

R15： Also called pc, Program counter , Always save the current address （ Pay attention to assembly line technology ） The address of the instruction . stay ARM State, , It differs from the address of the instruction currently being executed 8 Bytes （3 Class assembly line ）.

Status register

CPSR（ Current program status register ） Can be accessed in any processor mode , It contains conditional flag bits 、 Interrupt inhibit bit 、 The current processor mode flag and other control and status bits , The format is shown in the figure . Besides , There is also a dedicated physical status register for each exception mode , be called SPSR（ Backup program status register ）, When a particular exception occurs , This register is used to store CPSR The content of , When the exception mode returns , It can be used SPSR To restore CPSR.

• M： Processor mode bit , By modifying this section , You can switch the operating mode of the processor ;
• T： Identify whether you are currently using Thumb Instructions ,0 by ARM Command mode ,1 by Thumb Command mode ;
• F：FIQ Disable flag bit , If 1, Then disable FIQ,0 To open ;
• I： Allied , This is a IRQ Disable flag bit ;
• V：ALU Operation overflow flag ;
• C：ALU Carry mark ;
• Z：ALU Zero mark ;
• N：ALU negative ;

Instruction set

ARM The following commands are supported .

Instruction condition code

Almost all ARM Instructions can carry condition codes , Make the instruction execute only when the condition is satisfied , The supported condition codes are as follows ：