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Logisim group experiment 10 single cycle MIPS CPU

2022-07-24 16:45:00 SakamataZ

All circuits are already in educoder Platform test passed .
The circuit file has been hosted to Github, welcome star: Click here

mips Command format

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  • When OP When all six digits are zero , Said is R Type command
    Rs、Rt Original register ,Rd It's the target register
    shamt Is the offset used to shift , Maximum offset 31 position
    The last field funct Describe the operation function , Equivalent to op The extended opcode of the field 32 Representing addition ,34 Representation subtraction
  • OP Not for 0, Be able to uniquely identify different functions I Type instruction has two operands Rs and Rt

Instructions

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lw:

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addi:
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sw:
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beq:
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bne:
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add:

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syscall:
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slt:
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Auxiliary instructions R_TYPE:
Used to determine whether it is a register write back signal

Instruction decoding logic

OP It's an instruction 26-31 position ,func It's an instruction 0-5 position .
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ALU Control logic

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ALU_OP=(( Instructions ==slt)?11:5)

Control signals

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Circuit diagram

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Functional specifications

Support 8 strip MIPS Core instruction , The final design realizes MIPS The processor can run bubble sort test program sort.asm, The program is automatically stored in the data memory 0~15 Write 16 Data , Then use bubble sort to sort the data in ascending order .

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