[parallel and distributed systems] cache learning

Cache The basic principle of

We share 8 That's ok cache line,cache line Size is 8 Bytes. So we can take advantage of the low address 3 bits（ As shown in the blue part of the address above ） Used to address 8 bytes A byte in the , We call this part bit Combination for offset. Empathy ,8 That's ok cache line, To cover all rows . We need to 3 bits（ As shown in the figure above, the yellow part of the address ） Find a row , This part of the address is called index. Now we know that , If two different addresses , Of its address bit3-bit5 If exactly the same , Then the two addresses will find the same after hardware hashing cache line. therefore , When we find cache line after , It only represents the data corresponding to the address we access. There may be this cache line in , But it may also be the data corresponding to other addresses . therefore , We introduce tag array Area ,tag array and data array One-to-one correspondence . every last cache line All correspond to the only one tag,tag The whole address bit width is saved in index and offset The use of bit rest （ As shown in the figure above, the green part of the address ）.tag、index and offset The combination of the three can uniquely determine an address . therefore , When we according to the address index A find cache line after , Take out the current cache line Corresponding tag, And then... In the address tag Compare , If equal , This explanation cache hit . If it's not equal , Show the current cache line It stores data from other addresses , This is it. cache defect . In the figure above , We see tag The value of is 0x19, And... In the address tag Partially equal , So this visit will hit . because tag The introduction of , So it answers our previous question “ Why hardware cache line Not made into a byte ？”. This will lead to an increase in hardware costs , Because the original 8 One byte corresponds to one tag, Now need 8 individual tag, Takes up a lot of memory .tag It's also cache Part of , But we talked about cache size I don't think about tag The part of memory occupied .

We can see from the picture tag There's another one next to it valid bit, This bit Used to represent cache line Whether the data in is valid （ for example ：1 Means effective ;0 Is invalid ）. When the system just started ,cache The data in should be invalid , Because you haven't cached any data yet .cache The controller can be controlled according to valid bit Confirm current cache line Is the data valid . therefore , The above comparison tag confirm cache line It will also be checked before hitting valid bit Whether it works . Only if it works , Compare tag It makes sense . If an invalid , Direct determination cache defect .


In the example above ,cache size yes 64 Bytes also cache line size yes 8 bytes.offset、index and tag Separate use 3 bits、3 bits and 42 bits（ Suppose the address width is 48 bits）. Now let's look at another example ：512 Bytes cache size,64 Bytes cache line size. According to the previous address division method ,offset、index and tag Separate use 6 bits、3 bits and 39 bits. As shown in the figure below .