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System Verilog common syntax

2022-07-29 01:05:00 【qq_ thirty-two million seven hundred and fifty-two thousand eig】

Simulation display state machine ascii

enum logic [3:0] {IDLE=4’d0,STEP1=4’d1,STEP2=4’d2} cur_sta,next_sta;

Defining structure 

typedef struct packed{
    
reg [5:0]   a  ;
reg [5:0]   b  ;
}   spi_cmd    ;
logic    [3:0]  [$bits(spi_cmd )-1:0]   data   ;
spi_cmd  [3:0]                          data   ;
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