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Exercise 8 Chapter 8 Verilog finite state machine design -4 Verilog quartus Modelsim
2022-06-29 20:27:00 【51CTO】
4. Design traffic light controller with state machine , The design requirements ：A Luhe B road , Every road has a red 、 yellow 、 Green three lights , Duration is ： A red light 45s, Yellow light 5s, A green light 40 second .
A Luhe B The state transition of street lamp is ：
（1） A red ,B green （ The duration of the 40s）;
（2） A red ,B yellow （ The duration of the 5s）;
（1） A green ,B red （ The duration of the 40s）;
（1） A green ,B yellow （ The duration of the 5s）;
4.1 Design thinking ：
From the question, we know that there are 4 Status , The duration of each state and its output is 40s or 5 second . Therefore, a mold is designed as 90 The counter of , branch 4 paragraph , Continuous for each state
Time , Then the sequence loops .
4.2 The source code of two-way traffic light control circuit is as follows ：
1 //triffic lights
2 //ex8_4
3 //2020-10-14
4 //by YongFengXie
5 module ex8_4(clk,rst_n,lights);
6 input clk;
7 input rst_n;
8 output reg [5:0] lights; //A and B light
9
10 reg [6:0] cnt; // counter 90
11 reg [3:0] state;
12
13 parameter s0=4'b0001,s1=4'b0010,s2=4'b0100,
14 s3=4'b1000;
15
16 always @(posedge clk or negedge rst_n)
17 begin
18 if(!rst_n)
19 cnt<=7'd0;
20 else if(cnt<7'd90)
21 cnt<=cnt+1'b1;
22 else
23 cnt<=7'd0;
24 end
25
26 always @(posedge clk or negedge rst_n)
27 begin
28 if(!rst_n)
29 begin
30 state<=s0;
31 lights<=6'b100_001;
32 end
33 else if(cnt<7'd40)
34 begin
35 state<=s0;
36 lights<=6'b100_001; //RYG(A)_RYG(B)
37 end
38 else if(cnt>7'd39 &&cnt<7'd45)
39 begin
40 state<=s1;
41 lights<=6'b100_010; //RYG(A)_RYG(B)
42 end
43 else if(cnt>7'd44 && cnt<7'd85)
44 begin
45 state<=s2;
46 lights<=6'b001_100; //RYG(A)_RYG(B)
47 end
48 else
49 begin
50 state<=s3;
51 lights<=6'b001_010; //RYG(A)_RYG(B)
52 end
53 end
54
55 endmodule
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4.3 Test code of traffic light controller ：
1 //ex8_4 testbench
2 //2020-10-14
3 //by YongFengXie
4 `timescale 1ns/1ns
5 module ex8_4tb;
6 reg clk;
7 reg rst_n;
8 wire [5:0] lights;
9
10 ex8_4 ub(clk,rst_n,lights);
11
12 initial begin
13 clk=1'b0;
14 rst_n=1'b0;
15 #20 rst_n=1'b1;
16 #1000 $stop;
17 end
18
19 always #5 clk=~clk;
20
21 endmodule
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4.4 The simulation results of the traffic light controller are shown in Figure ex8_4_1 Shown ：
chart ex8_4_1 Traffic light controller simulation results
4.5 summary ： The state transition of the traffic light controller circuit is very simple , The title has been listed in detail . The difficulty is that the duration of each state is different , This is different from the previous sequence detection Fang . According to the above design , stay Quartus No state transition diagram is generated in , Simulation and DE2-115 Can be verified to be correct . Looking forward to a better solution .
4.6 reference , Find a way , Timing module , State transition , State output , Write clearly and separately , The difficulty lies in The counter still only needs one , The control mode is different , Produce the effect of timing , That's what we need 40s,5s Time of , In the design, a flag is generated when the state changes st, meanwhile This st, In the timing module, it plays a function of clearing the counter , Reach the timing to different values , The counter is cleared to restart counting , Seemingly useless st, Correlator state changes
The rhythm of .
Another kind of traffic light controller Verilog The code is as follows ：
1 //triffic lights
2 //ex8_4
3 //2020-10-14
4 //by YongFengXie
5 module ex8_4(clk,rst_n,lights);
6 input clk;
7 input rst_n;
8 output reg [5:0] lights; //A and B light
9
10 reg [6:0] cnt; // counter 90
11 reg [3:0] state,nextstate;
12 wire t1,t2; // t1-40s,t2-5s
13 reg st; // state transition signal
14
15 parameter s0=4'b0001,s1=4'b0010,s2=4'b0100,
16 s3=4'b1000;
17
18 //timing module
19 always @(posedge clk or negedge rst_n)
20 begin
21 if(!rst_n)
22 cnt<=7'd0;
23 else if(st)
24 cnt<=7'd0;
25 else if(cnt<7'd40)
26 cnt<=cnt+1'b1;
27 else
28 cnt<=7'd0;
29 end
30
31 assign t1=(cnt==7'd39)?1'b1:1'b0;
32 assign t2=(cnt==7'd4)?1'b1:1'b0;
33
34 /*
35 always @(posedge clk or negedge rst_n)
36 begin
37 if(!rst_n)
38 begin
39 state<=s0;
40 lights<=6'b100_001;
41 end
42 else if(cnt<7'd40)
43 begin
44 state<=s0;
45 lights<=6'b100_001; //RYG(A)_RYG(B)
46 end
47 else if(cnt>7'd39 &&cnt<7'd45)
48 begin
49 state<=s1;
50 lights<=6'b100_010; //RYG(A)_RYG(B)
51 end
52 else if(cnt>7'd44 && cnt<7'd85)
53 begin
54 state<=s2;
55 lights<=6'b001_100; //RYG(A)_RYG(B)
56 end
57 else
58 begin
59 state<=s3;
60 lights<=6'b001_010; //RYG(A)_RYG(B)
61 end
62 end
63 */
64
65 //state transition module
66 always @(posedge clk or negedge rst_n)
67 begin
68 if(!rst_n)
69 state<=s0;
70 else
71 state<=nextstate;
72 end
73
74 always @(state,t1,t2)
75 begin
76 case(state)
77 s0: begin
78 nextstate<=t1?s1:s0;
79 st<=t1?1'b1:1'b0;
80 end
81 s1: begin
82 nextstate<=t2?s2:s1;
83 st<=t2?1'b1:1'b0;
84 end
85 s2: begin
86 nextstate<=t1?s3:s2;
87 st<=t1?1'b1:1'b0;
88 end
89 s3: begin
90 nextstate<=t2?s0:s3;
91 st<=t2?1'b1:1'b0;
92 end
93 default: begin
94 nextstate<=s0;
95 st<=1'b0;
96 end
97 endcase
98 end
99
100 //state corresponding output
101 always @(state)
102 begin
103 case(state)
104 s0:lights=6'b100_001; //A-R,B-G
105 s1:lights=6'b100_010; //A-R,B-Y
106 s2:lights=6'b001_100; //A-G,B-R
107 s3:lights=6'b010_100; //A-Y,B-R
108 default:lights=6'b100_001; //A-R,B-G
109 endcase
110 end
111
112 endmodule
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The code above is not concise enough , There is still a problem of fixed thinking , From which 18 The timing module at the beginning of the line is better made into a variable modulus counter , therefore , This paragraph , Revised as follows ：
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