Hc32f4a0 clock control

																 HC32F4     The control of the clock 

The following clock control is subject to the official reference routine , Set the specific frequency by yourself ：
1. If you do not initialize the clock , The default is the internal medium speed clock 8MHZ, All clocks are 8MHZ. Power on initialization adjustment use system_hc32f4a0.c Inside SystemCoreClockUpdate() function , Initialize the clock .
void SystemCoreClockUpdate(void)
{
…
tmp = M4_CMU->CKSWR & CMU_CKSWR_CKSW;
switch(tmp) // tmp = 1
{
case 0x00U: /* use internal high speed RC /
SystemCoreClock = HRC_VALUE;
break;
case 0x01U: / use internal middle speed RC /
SystemCoreClock = MRC_VALUE; // Call this branch
break;
case 0x02U: / use internal low speed RC */
SystemCoreClock = LRC_VALUE;
break;
…
}
}

2. With usart Under the folder usart_polling Take the routine in the project as an example , Explain ：
void BSP_CLK_Init(void)
{
stc_clk_xtal_init_t stcXtalInit;
stc_clk_pllh_init_t stcPLLHInit;

/* PCLK0, HCLK  Max 240MHz */
/* PCLK1, PCLK4 Max 120MHz */
/* PCLK2, PCLK3 Max 60MHz  */
/* EX BUS Max 120MHz */
CLK_ClkDiv(CLK_CATE_ALL,                                                   \
           (CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 |             \
            CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 |             \
            CLK_HCLK_DIV1));

CLK_XtalStructInit(&stcXtalInit);
/* Config Xtal and enable Xtal */
stcXtalInit.u8XtalMode = CLK_XTALMODE_OSC;
stcXtalInit.u8XtalDrv = CLK_XTALDRV_LOW; 			  //   Low speed external clock 
stcXtalInit.u8XtalState = CLK_XTAL_ON;  					  //    Turn on the external clock 
stcXtalInit.u8XtalStb = CLK_XTALSTB_2MS;
CLK_XtalInit(&stcXtalInit); 										   //  Reconfigure to external clock 

(void)CLK_PLLHStructInit(&stcPLLHInit);
/* VCO = (8/1)*120 = 960MHz*/
stcPLLHInit.u8PLLState = CLK_PLLH_ON;
stcPLLHInit.PLLCFGR = 0UL;
stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLN = 120UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLLSRC_XTAL;
(void)CLK_PLLHInit(&stcPLLHInit);						// Reconfigure parameters 

… Omit

CLK_SetSysClkSrc(CLK_SYSCLKSOURCE_PLLH);    Call the initialization clock 

}
Call the following function again
void CLK_SetSysClkSrc(uint8_t u8Src)
{
…
SystemCoreClockUpdate();
}
By calling again SystemCoreClockUpdate(); Complete the initialization of the external clock configuration ：
void SystemCoreClockUpdate(void)
{
…

tmp = M4_CMU->CKSWR & CMU_CKSWR_CKSW;
switch(tmp)                                                                              //  tmp = 5
{
  ....................
    case 0x05U:  /* use PLLH */
        /* PLLCLK = ((pllsrc / pllm) * plln) / pllp */
        pllp = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHP_POS) & 0x0FUL);
        plln = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHN_POS) & 0xFFUL);
        pllm = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHM_POS) & 0x03UL);

        /* use external high speed OSC as PLL source */
        if (0UL == bM4_CMU->PLLHCFGR_b.PLLSRC)
        {
            SystemCoreClock = (XTAL_VALUE) / (pllm + 1UL) * (plln + 1UL) / (pllp + 1UL);                 //  SystemCoreClock =  240 MHZ
        }
        /* use internal high RC as PLL source */
        else
        {
            SystemCoreClock = (HRC_VALUE) / (pllm + 1UL) * (plln + 1UL) / (pllp + 1UL);
        }
        break;
    default:
        break;
}

}
Get the system clock is ：ystemCoreClock = 240 MHZ

Through frequency division function CLK_ClkDiv(CLK_CATE_ALL,
(CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 |
CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 |
CLK_HCLK_DIV1));

You can reach the following frequencies ,
/* PCLK0, HCLK Max 240MHz /
/ PCLK1, PCLK4 Max 120MHz /
/ PCLK2, PCLK3 Max 60MHz */

3. You can also use CLK_GetClockFreq(); Get the frequency of each clock source
stc_clk_freq_t CklFreq;
CLK_GetClockFreq(&CklFreq);
en_result_t CLK_GetClockFreq(stc_clk_freq_t *pstcClkFreq)
{
en_result_t enRet = Ok;
uint32_t plln;
uint32_t pllp;
uint32_t pllm;

if (NULL == pstcClkFreq)
{
    enRet = ErrorInvalidParameter;
}
else
{
    switch (READ_REG8_BIT(M4_CMU->CKSWR, CMU_CKSWR_CKSW))
    {
        case CLK_SYSCLKSOURCE_HRC:
            /* HRC is used to system clock */
            pstcClkFreq->sysclkFreq = HRC_VALUE;
            break;
        case CLK_SYSCLKSOURCE_MRC:
            /* MRC is used to system clock */
            pstcClkFreq->sysclkFreq = MRC_VALUE;
            break;
        case CLK_SYSCLKSOURCE_LRC:
            /* LRC is used to system clock */
            pstcClkFreq->sysclkFreq = LRC_VALUE;
            break;
        case CLK_SYSCLKSOURCE_XTAL:
            /* XTAL is used to system clock */
            pstcClkFreq->sysclkFreq = XTAL_VALUE;
            break;
        case CLK_SYSCLKSOURCE_XTAL32:
            /* XTAL32 is used to system clock */
            pstcClkFreq->sysclkFreq = HRC_VALUE;
            break;
        case CLK_SYSCLKSOURCE_PLLH:
            /* PLLHP is used as system clock. */
            pllp = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHP_POS) & 0x0FUL);
            plln = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHN_POS) & 0xFFUL);
            pllm = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHM_POS) & 0x03UL);

            /* fpll = ((pllin / pllm) * plln) / pllp */
            if (CLK_PLLSRC_XTAL == READ_REG32_BIT(M4_CMU->PLLHCFGR, CMU_PLLHCFGR_PLLSRC))
            {
                pstcClkFreq->sysclkFreq = ((XTAL_VALUE/(pllm + 1UL))*(plln + 1UL))/(pllp + 1UL);
            }
            else
            {
                pstcClkFreq->sysclkFreq = ((HRC_VALUE/(pllm + 1UL))*(plln + 1UL))/(pllp + 1UL);
            }
            break;
        default:
            break;
    }

    /* Get hclk. */
    pstcClkFreq->hclkFreq = pstcClkFreq->sysclkFreq >> \
                (READ_REG32_BIT(M4_CMU->SCFGR, CMU_SCFGR_HCLKS) >> CMU_SCFGR_HCLKS_POS);

    /* Get exck. */
    pstcClkFreq->exckFreq = pstcClkFreq->sysclkFreq >> \
                (READ_REG32_BIT(M4_CMU->SCFGR, CMU_SCFGR_EXCKS) >> CMU_SCFGR_EXCKS_POS);

    /* Get pclk0. */
    pstcClkFreq->pclk0Freq = pstcClkFreq->sysclkFreq >> \
                (READ_REG32_BIT(M4_CMU->SCFGR, CMU_SCFGR_PCLK0S) >> CMU_SCFGR_PCLK0S_POS);

    /* Get pclk1. */
    pstcClkFreq->pclk1Freq = pstcClkFreq->sysclkFreq >> \
                (READ_REG32_BIT(M4_CMU->SCFGR, CMU_SCFGR_PCLK1S) >> CMU_SCFGR_PCLK1S_POS);

    /* Get pclk2. */
    pstcClkFreq->pclk2Freq = pstcClkFreq->sysclkFreq >> \
                (READ_REG32_BIT(M4_CMU->SCFGR, CMU_SCFGR_PCLK2S) >> CMU_SCFGR_PCLK2S_POS);

    /* Get pclk3. */
    pstcClkFreq->pclk3Freq = pstcClkFreq->sysclkFreq >> \
                (READ_REG32_BIT(M4_CMU->SCFGR, CMU_SCFGR_PCLK3S) >> CMU_SCFGR_PCLK3S_POS);

    /* Get pclk4. */
    pstcClkFreq->pclk4Freq = pstcClkFreq->sysclkFreq >> \
                (READ_REG32_BIT(M4_CMU->SCFGR, CMU_SCFGR_PCLK4S) >> CMU_SCFGR_PCLK4S_POS);
}
return enRet;

}

4. All the above reference functions are simulated in one step , The data is true and valid , I hope I can help you .