Detailed explanation of makefile usage

Previously introduced gcc 了 , This article is mainly in gcc Later, in order to facilitate the compilation of the file ！

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This chapter is divided into two parts ：             Makefile The basic way of writing         Makefile Variable substitution writing

No more nonsense , Let's go straight to work ！

Makefile The basic way of writing ：

The following documents are included in the project ：（ For program content, please refer to atomic brother Makefile chapter ！） 

By the previous gcc You know , We can compile directly , But trouble , So we're right now Makefike Documents are written （ The name should be Makefile！）, The contents are as follows ：

ljs: main.o input.o calcu.o 
	gcc -o ljs main.o input.o calcu.o 
main.o: main.c
	gcc -c main.c
input.o: input.c
	gcc -c input.c
calcu.o: calcu.c
	gcc -c calcu.c
clean: 
	rm *.o
	rm ljs

The code analysis ： Do the following make

Executable file ljs Depend on these three .o file , And then for these three .o File for compilation

                main.o Depend on main.c. Then on main.c Compile

  The code analysis ： Do the following make clean

    

  Through the above Makefile Set up , So after we change one of the programs , The system will only compile the changed , What has not been modified will not change , give the result as follows ：

summary ： This kind of writing is easy to understand , But it's more troublesome , The variable substitution described below will be simpler ！

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Makefile Variable substitution                 How to write it ：

 

Program analysis ： Set string main.o input.o calcu.o And assign it to objects

                $ Is the prefix of a variable , That is to say ljs Dependent on variables objects

                %.c Express all .c file

                Like everything else

On the file make and make clean You can get the same effect .