How to realize clock signal frequency division?

        In the digital circuit experiment , It is often necessary to divide the clock signal , To realize the output of clock signals with different frequencies .

         The following question is an example ： The request will 50MHz Divide the clock signal of , produce 1MHz The clock signal of . Its Verilog Described below ：       

         First , Accurately understand 50MHz What is the concept of clock frequency ？ 

       

        50MHz The clock signal of , Its period is 1/50M second ,1 Second has 50M Square wave signal . 

module example(clk_out,clk_in);
  output reg clk_out;
  input clk_in;
  reg [30:0]cnt;
  [email protected](posedge clk_in)
  begin
    if(cnt==24999999)
	 begin
	   clk_out<=!clk_out;
		cnt<=0;
    end
	 else
	   cnt<=cnt+1;
  end
endmodule

        The port list is very simple , There is only one input clock signal and one output clock signal .

        50MHZ÷1HZ=50000000, Then you can 50MHZ The clock signal of , Set initial value cnt=0. Count when cnt Don't reach 50000000/2 namely 25000000 When the time ,cnt Self increasing 1;

        Count when cnt achieve 50000000/2 namely 25000000 When the time .clo_out <= ~clkout, That is, flipping , also cnt from 0 Start counting again .

         This can be achieved repeatedly clk_out The output signal of is 1HZ. 

        The end of this article , If there is any deficiency , Welcome to exchange ！