FPGA first try

quartus II Fallible

To write verilog Language and compile

module The name should be the same as the file name , The name should be the same as the project name , It's not easy to make mistakes

modelsim Simulation

Add again testbench, Write your own simulation program

modelSim Repetitive simulation

Suppose you modify testBench Program file or component program , To recompile

Select the two files to recompile , Recompile
Then open the simulation file


Pull to the bottom work Inside testBench file , Then determine

Then the leftmost instance Where? ,ctrl+w Add waveform , then

restart and run Conduct simulation . Remember that the middle is the total length of time

Analog waveform output decimal

Course design source code

module xiyiji
#(
        parameter set_cnt_min = 25'd10
)
(
        input wire sys_clk,
        input wire sys_work,
        output wire [24:0] out_sec,
        output wire [24:0] out_min,
        output wire [0:0] is_finish
);
        reg [24:0] cnt_sec=25'd20;
        reg [24:0] state=25'd0;
        reg [24:0] cnt_min=set_cnt_min;
        always @(posedge sys_clk or negedge sys_work)
                
                if(sys_work==1'b0)begin
                        // Set to initial value when not working 
                        cnt_sec<=25'd20;
                        state<=25'd0;
                        cnt_min<=set_cnt_min;
                end
                else if(cnt_min==25'd0)begin
                        cnt_min<=cnt_min;
                        cnt_sec<=25'd0;
                        state<=25'd0;
                end
                else if(cnt_sec==25'd0)begin
                        if(state==25'd3&&cnt_min==25'd1)begin
                                // It's over 
                                state<=25'd0;
                                cnt_min<=25'd0;
                                cnt_sec<=25'd0;
                        end
                        else if(state==25'd3)begin
                                // A reincarnation is over 
                                state<=25'd0;
                                cnt_min<=cnt_min-25'd1;
                        end
                        else begin
                                // Jump from one intermediate state to another intermediate state 
                                state<=state+25'd1;                
                        
                        end
                        cnt_sec<=(state==25'd1||state==25'd3)?25'd19:25'd9;
                end
                else begin
                        cnt_sec<=cnt_sec-25'd1;
                end
        assign out_sec=cnt_sec;
        assign out_min=cnt_min;
        assign is_finis=(cnt_min==25'd0)?1'b1:1'b0;


endmodule

`timescale  10ns/1ns
module  tb_led();

reg sys_clk;
reg sys_work;
wire [24:0] out_sec;
wire [24:0] out_min;
wire [0:0] is_finish;

initial
    begin
        sys_clk=1'b1;
        sys_work<=1'b0;
        #20
        sys_work<=1'b1;
    end    
always #10 sys_clk=~sys_clk;
xiyiji 
#(
    .set_cnt_min(25'd8)
)
xiyijiInst(
.sys_clk(sys_clk),
.sys_work(sys_work),
.out_sec(out_sec),
.out_min(out_min),
.is_finish(is_finish)
);

endmodule