Mastering JESD204B (1) – Debugging of AD6676

Mastering JESD204B (1)-AD6676 debugging

Hardware Platform Description

The hardware platform mainly includes:

1. Virtex7:690T-FFG1761;
2. Zynq:XC7Z015-CLG485;
3. AD chip: AD6676;
4. Clock Chip: HMC7044.

System Requirements

The system mainly completes the configuration of the clock chip, completes the acquisition of 4 pieces of AD6676, and uploads the collected data through the Zynq network, and uploads it to the host computer and saves it as a file for subsequent data processing;

System part hardware diagram design

1. Clock Design Section

1. AD6676 hardware design
   
2. FPGA receiving data hardware design

The next chapter will continue to explain the configuration of 204B