[datasheet] PHY ksz9031 gigabit network chip interpretation

1、 characteristic

have RGMII Gigabit Ethernet transceivers supported , Single chip 10/100/1000Mbps Ethernet transceiver , Apply to IEEE 802.3 application ; It is widely used in network servers 、 Broadband gateway 、IPTV、 Game console, etc ;

Working voltage ：

- kernel （DVDDL、AVDDL and AVDDL_PLL）1.2V

-VDD I/O(DVDDH): 3.3V、2.5V and 1.8V

- Transceiver (AVDDH):3.3V or 2.5V

-PHY Register configuration MDC/MDIO Management interface

If in Linux Debug this PHY Chip drivers , First of all, we should find out the chip manufacturers ,Micrel Chips produced by the company , After being MICROCHIP Company purchase ; The kernel path is drivers/net/phy/micrel.c;

PHY Introduction to the use of chips ,MCU You need to bring it with you MAC controller , We often say that the network card chip is encapsulated MAC+PHY function , Through the bus or SPI Interface for users ;

MAC And PHY How to communicate with each other ,PHY Register read / write parameter configuration , adopt MDC/MDIO To operate , The sequence is 32 Bit serial timing , It's usually MAC Integrate ; Data flow through RGMII/RMII/MII Media interface transmission ;

We will talk about it later PHY Address configuration ,MAC Conduct PHY Register read and write , The first thing to know is PHY The hardware address of , The address can be configured through the circuit ;

As a Gigabit Network , Hardware requirements RGMII Interface application , Provide 125MHZ Reference clock signal , Use 4 Two differential pairs A（ Pin 2 and 3）、B（ Pin 5 and 6）、C（ Pin 8 and 9）、D（ Pin 10 and 11）;

As a 100m network , Use MII Interface ,25MHZ Reference clock signal , Use only differential pairs A and B; The difference is right C and D Can be left unconnected ;

Here's the key MII Management interface （MII Management）

Integrated clock line （MDC） And data lines （MDIO） The physical connection of ;

As mentioned above PHY Address , Every PHY Device pass PHYAD[2:0] Configure pins 0~7H Assign a unique address between ; according to PHY Address , But for PHY Register programming ;

Every frame 32 position Bit, among PHY The register is 16 Bit data , Each register is fixed bit 16 position ;

MII Debugging skills ： Read PHY Identifier register , There is solidified manufacturer information , Compare with the chip manual , Verifiable MII Whether the communication is normal ;

LED Module programmable , We often talk about link state and active state , Through software programming, the roles of the two lights can be interchanged ;

Reset circuit

The reset circuit of this chip is very special , But debugging this chip because the hardware uses the wrong capacitor （ Partial ）, As a result, the power on chip cannot be reset , The kernel startup process always fails to find the chip , Profound memory ;

Supported by PHY The register is shown in the following table ：

The pin diagram is as follows ：

Pin definitions are shown in the following table ：

You are welcome to criticize and correct your mistakes , We will share later Linux Drive commissioning experience ;

Pay attention to WeChat public number , reply ksz9031, Chinese chip manual is free to download ;