Power consumption: leakage power

1 CMOS circuit Power classification ：

1. Static power supply
2. Dynamic power

Static power is the power consumed when the circuit is inactive or idle . That is, all inputs are at the hold active level , No switch activity , And the circuit is not charged . However , Even in this “ Steady state ” Next , There will also be some leakage current in the device , This will cause leakage power . This power consumption does not depend on input conditions or load capacitance , It depends on the device .

2 Leakage source

1）Reverse bias-pn junction leakage current
2）Subthreshold leakage current

• Drain-induced barrier lowering
• Vth roll off
• Effect of operating temperature
• Tunneling into and through gate oxide leakage current
• Leakage current due to hot carrier injection from the substrate to gate oxide
• Leakage current due to gate-induced drain lowering (GIDL)

3 How to reduce dynamic power consumption by clock gating

3.1 Clock gating reduces flipping

The gated clock will drive the clock DFF Because there is no clock drive, there will be no inversion , Reduce the flip power consumption of the circuit , The dynamic power consumption is significantly reduced .

3.2 Clock gated pair DFF The parasitic capacitor of the register makes a sound when charging and discharging

The clock will be on every DFF Parasitic capacitance is generated on the register , Parasitic capacitance will produce charge and discharge process in the process of clock reversal , Need to draw current from the power supply , Thus generating power consumption . And clock gating can be avoided DFF Charging and discharging process of parasitic capacitance , Avoid such power consumption .