Implementation and Simulation of ads131a04 ADC Verilog

ADS13104：datasheet

The state machine diagram ：

ADC And FPGA Communication schematic diagram ：
FPGA Internally integrated with a SPI MASTER controller , Responsible for and ADC The chip communicates .
sampling frequency ： 5120Hz 10240Hz ,ARM The processor can use SPI Interface setting sampling frequency .

stay vivado On the implementation of ：

Simulation screenshot ：

verilog The design code is as follows ：

module ADC_MODULE(
input clk,//62.5ns
input rst_n,
output sclk,
output reg cs_n,
output reg mosi,
output reg[47:0] receive_data,
input miso,
output reg[7:0] bit_cnt,<