Quartus call & design D trigger Simulation & timing wave verification

Catalog

1、 stay Quartus-II I use the gate circuit to design a D trigger , And simulate , Timing waveform verification ;
2、 stay Quartus-II Directly call a D Trigger circuit , Conduct simulation , Timing waveform verification , And 2 compare ;
3、 stay Quartus-II use Verilog Write a language D trigger , Conduct simulation verification

One 、 know D trigger

D A trigger is a device with memory function , Information storage device with two stable states , Is to constitute a variety of The most basic logic unit of a sequential circuit , It is also an important unit circuit in digital logic circuit .
D Trigger in Clock pulses CP The leading edge of the （ Positive jump 0→1） Flipping occurs , The secondary state of the trigger depends on CP Before the rising edge of the pulse arrives D The state of the end , namely Substate =D. therefore , It has 0、 Set up 1 Two functions . Because in CP=1 During this period, the circuit has the function of maintaining blocking , So in CP=1 period ,D The data state of the terminal changes , It will not affect the output state of the trigger .
D Triggers are widely used , It can be used as the deposit of digital signals , Shift deposit , Frequency division and waveform generator, etc .

1、 structure

D trigger （data flip-flop or delay flip-flop） from 4 A NAND gate , among G1 and G2 Constitute the basic RS trigger . When the level triggered master-slave trigger works , The input signal must be added before the positive jump edge . If in CP Interference signal appears at the input during high level , Then it is possible to make the trigger state error . The edge trigger allows you to CP The trigger edge comes to the moment before adding the input signal . such , The time when the input is disturbed is greatly shortened , The possibility of interference is reduced . edge D Triggers are also called sustain - Blocking edges D trigger . edge D The trigger can consist of two D The trigger is connected in series , But the first one D Trigger CP Need to use non gate reverse .

2、 features

Menu

Sequence diagram

This is right D A brief introduction to triggers , For more D Understanding of triggers , You can refer to the following link ;
D trigger .

Two 、 Design D Trigger timing verification

1、 Create a project

file—>new project wizard

Edit project name , Click later next

Choose the right chip and its family

direct next

Project creation complete , Click on finish

2、 Create a box file

Click on new

Select the signature in the red box

Select... As shown

choice nand2, Two input NAND gates , Add... In turn 4 individual nand2 And a non gate not

After adding, as shown in the figure

Select the connection tool

The wiring effect is shown in the figure （ Double click the mouse to change the pin name ）

Save the circuit diagram

3、 Compile schematic file

Compile the circuit diagram

Compiler interface

rtl viewer, Check the hardware circuit diagram

Circuit diagram

4、 establish vwm Waveform file

Select the icon vwm

Operation as shown in figure

add to node or bus

Effect display

Edit input signal clk, Generate a clock signal

Mouse selection D,Q The signal Q_n, Editing （ Select with the left mouse button Double click to change the value ）

5、 Timing waveform simulation

compile

There is an error

Connect modelsim


Error reporting solution


The result is shown in Fig.

Simulation results

3、 ... and 、 call D Trigger timing verification

1、 Create a box file

The creation method is the same as above
call D trigger

Wiring patch pin , The effect is as shown in the picture （Ctrl+ The mouse wheel can zoom the trigger pin, etc ）

2、 Compile the schematic

Check the hardware diagram

compile

3、 establish vwm Waveform file and simulation

wave form

Timing simulation results

Four 、verilog Language implementation D Trigger timing verification

1、 To write verilog file

Create the project first , Method is the same as above.
establish Verilog file , Click on file—new

Paste the following code

//demo File name 
module demo(d,clk,q);
    input d;
    input clk;
    output q;

    reg q;

    always @ (posedge clk)// We use the positive edge of the clock as its sensitive signal 
    begin
        q <= d;// When the rising edge is valid , hold d Capture to q
    end
endmodule

Save and compile

2、 View the generated circuit diagram

3、 Test timing simulation

The code is as follows

// Test code 
`timescale 1ns / 1ns

module demo_tb;
    reg clk,d;
    wire q;

    demo u1(.d(d),.clk(clk),.q(q));

    initial
    begin
        clk = 1;
        d <= 0;
        forever
        begin
            #60 d <= 1;// Artificially generated burr  
            #22 d <= 0;
            #2 d <= 1;
            #2 d <= 0;
            #16 d <= 0;// maintain 16ns Low level of , Then let it cycle periodically 
        end
    end

    always #20 clk <= ~clk;// Half cycle is 20ns, The whole cycle is 40ns A signal of 
endmodule

Save and compile

Simulation effect picture

5、 ... and 、 Summary and references

1、 summary

D The process of trigger timing simulation , You can find D The basic function of the trigger is when the reset signal is 1 When ,CLK The rising edge of will cause Q Change in value . thus , It can be concluded that the equation of state is Q n + 1 = D

2、 Reference material

Quartus II Use of built-in simulation tools .
Quartus-II Input schematic diagram and simulation steps .docx.
Quartus-II13.1 Three ways to achieve D Trigger timing simulation .