[FPGA]: Joint Simulation of FPGA and MATLAB

One 、 matlab End operation

1.1 matlab Read in the data

file_name ： txt The name of the file
file_path： File storage path
The following code is ,txt Three columns in text , Read out three columns at the same time

%% matlab Read modelsim Generated documents 、
clear all;
clc;
file_name = 'data_out_1';
file_path = ['E:\vivado_project\', file_name, '.txt'];
file_id = fopen(file_path);
data = textscan(file_id, '%s%s%s');
fclose(file_id);
for i=1:3
    C_double(i,:)= str2double(data {
    1,i});
end

1.2 matlab Save the data

%% matlab Save the file as txt
N=256;
n=1:N;
f0=100;
fs=500;
data = round(256+255*sin(2*pi*f0/fs*n));
fid = fopen('sin.txt','w');
fprintf(fid,'%x\n',data);  % x representative 16 Base number   d For decimal 
fclose(fid);

Two 、 modelsim End operation （verilog）

2.1 modelsim Read in of

readmemh: read 16 Hexadecimal data
readmemb: read 2 Hexadecimal data

wire rst;
reg [7:0] data,i ;
reg [7:0] data_mem[255:0];
initial begin
    $readmemh("sin.txt",data_mem); 
end
[email protected](posedge clk,posedge rst) begin
    if(rst) begin
        data <= 8'd0;
        i<=8'd0;
    end
    else begin
       data<= data_mem[i];
       i <= i+1; 
   end 
end

The code for reading decimal is as follows ;

reg rst;
reg [7:0] data,i ;
reg signed [7:0] data_mem[255:0];
integer fid1,s;
initial begin
	fid1 = $fopen("C:/Users/Desktop/sin.txt","r");// The slash here is different from the slash in the computer , The slash in the computer is ‘\’, Here for ‘/’
	   for(i=0;i<=255;i=i+1) begin
	       #1;
	       s= $fscanf(fid1,"%d",data_mem[i]);
	   end
	    $fclose(fid1);
end

[email protected](posedge clk,posedge rst) begin
    if(rst) begin
        data <= 8'd0;
        i<=8'd0;
    end
    else begin
        data <= data_mem[i];
        i <= i+1; 
   end 
end

2.2 modelsim Output

i : Number of samples
#25: Sampling interval , It's related to the clock cycle
XXX： Signals to be intercepted
unsigned(XXX)： An unsigned number
signed(XXX)： Signed number

integer i;
integer w_file;
   initial begin
	 w_file = $fopen("data_out_1.txt");
         for(i=0;i<=8191;i=i+1)begin
	   #25; 
	   $fdisplay(w_file,"%d",$unsigned(XXX));% h representative 16 Base number  d For decimal 
	   if(i == 8191)
	   $fclose(w_file);
          end
    end  

among ：

$fdisplay：
This command requires trigger conditions , Will write the data to the file , As the above example [email protected](i), When i Data is written only when it changes , Every time the function finishes writing data, it will automatically add a line break , So a newline character will be added after the last data is written , Finally, we need to delete it ourselves , otherwise matlab Will read errors .

$fwrite:

Only when the trigger condition changes can the data be written into the file , But with the $fdisplay The difference is that line breaks are not automatically added every time data is written , We need to add our own .eg:always @ (i) $fwrite(w_file,”%h\n”,data_out);

$fmonitor:

This command is basically the same as $fdisplay identical , Only when the trigger condition changes can the data be written to the file ,eg：initial $fmonitor(w_file,”%h”,data_out);

3、 ... and 、 Reference material

【1】 Engineering gossip -ModelSim And Matlab file
【2】modelsim and matlab A combination of ( turn
【3】verilog Simulate the method of reading decimal data
【4】verilog Read in .txt Signed decimal number of , Write signed decimal numbers to .txt In file