Ram block memory generator of vivado IP core

Vivado IP Nuclear RAM Block Memery Generator

Catalog

Preface

One 、 Configuration steps

Two 、 Simulation

1. Top level code

2. Simulation code

3、 ... and 、 Simulation analysis

summary

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Preface

        This introduction vivado in RAM（Block Memery Generator）IP nucleus Use , I hope that's helpful .

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Tips ： The following is the main body of this article , All are original by the author , It's not easy to write an article , I hope you will attach a link to this article when reprinting .

One 、 Configuration steps

         stay vivado Mid search Block Memery Generator, To find the IP After the core, you can complete the corresponding configuration according to the following operations . This configuration is Single port mode .

        1. First configuration Basic Interface , Pictured 1 Shown .

        

chart 1 Basic Interface configuration

         2. Next configuration Port A Options Interface , Pictured 2 Shown .

chart 2 Port A Options Interface configuration

         3. Then configure Other Options Interface , Pictured 3 Shown . Here you can add initialization files , namely coe file , Used to initialize stored data .

chart 3 Other Options Interface configuration

         4. Finally, there is a Summary Interface , Pictured 4 Shown , We don't need to configure , A profile page .

chart 4 Summary Interface

          above 4 After all the interfaces are configured, you can click on the lower right corner OK Button generation IP nucleus .

Two 、 Simulation

1. Top level code

Build a top-level module , Name it ram_read, Used to instantiate the just generated IP nucleus .

The code is as follows ：

`timescale 1ns / 1ps
//
// Company: cq university
// Engineer: clg
// Create Date: 2022/07/27 16:43:07
// Design Name: 
// Module Name: ram_read
// Project Name: 
// Target Devices: 
// Tool Versions: 2017.4
// Description: 
// Dependencies: 
// Revision:1.0
// Revision 0.01 - File Created
// Additional Comments:
//
// Although it is ram, This time, we will ram When rom Use 
module ram_read(
    input clk,                    // Input clock signal 
    input rst_n,                  // Input reset signal 
    input start,                  // Input the start reading signal 
    input  [10 : 0] addr,         // Enter read address 
    input [31 : 0] din,           // Not used this time 
    output reg over,              // Output read data valid signal 
    output reg [31 : 0] dout      // Output the read data 
    );
//reg define
reg en;             // Read enable signal 
reg we;             // Reading and writing choices 
reg [1:0] cnt;      // Counter 
//wire define
wire [31:0] data;   // Reading data                  

always @(negedge clk or negedge rst_n)
begin
        if(!rst_n)
            cnt<=0;
        else if( (start==1)&(cnt<3))
            cnt<=cnt+1;
       else 
            cnt<=0;
end

always @(negedge clk or negedge rst_n) // Falling edge setting enable 
begin
        if(!rst_n)
            begin en<=0;we<=0;end
        else if(0<cnt<3)
            begin en<=1;we<=0;end
       else 
            begin en<=0;we<=0;end
end

always @(posedge clk or negedge rst_n)  // The rising edge reads stable data 
begin
        if(!rst_n)
            begin over<=0;dout<=0;end
        else if(cnt==3)
            begin over<=1;dout<=data;end
       else 
            begin over<=0;dout<=0;end
end

ram_sam_re_ip u1_ram_sam_re_ip (  // Exemplification ram
  .clka(clk),        // input wire clka
  .ena(en),          // input wire ena
  .wea(we),          // input wire [0 : 0] wea
  .addra(addr),      // input wire [10 : 0] addra
  .dina(din),        // input wire [31 : 0] dina
  .douta(data)       // output wire [31 : 0] douta
);


endmodule

2. Simulation code

Build a simulation module , Name it ram_read_tb, It is used to simulate the instantiation of the top-level module just now IP nucleus .

The code is as follows ：

`timescale 1ns / 1ps
//
// Company: cq university
// Engineer: clg
// Create Date: 2022/07/27 16:52:23
// Design Name: 
// Module Name: ram_read_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 2017.4
// Description: 
// Dependencies: 
// Revision:1.0
// Revision 0.01 - File Created
// Additional Comments:
//

module ram_read_tb();
reg clk;
reg rst_n;
reg start;
reg [10 : 0] addr;
reg [31 : 0] din;
wire over;
wire [31 : 0] dout;
    
ram_read u1_ram_read(
    .clk(clk),
    .rst_n(rst_n),
    .start(start),
    .over(over),
    .addr(addr),
    .din(din),
    .dout(dout)
    );
always #5 clk=~clk;
    initial begin
        clk=1'b0;rst_n=1'b1;
#5;     rst_n=1'b0;
#15;   rst_n=1'b1;
          start=1'b1;
          addr=11'd0;
#30   start=1'b0;
   end
    
endmodule

3、 ... and 、 Simulation analysis

         Some initial stored data are shown in the figure 5 Shown ,  The simulation results are shown in the figure 6 Shown , It can be seen that the simulation results are correct , Successfully read the address 0 The data of , Due to output buffer , So there's a delay .

chart 5  Some initial storage data

chart 6 Simulation results

 

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summary

This is the introduction , A brief introduction vivado in RAM IP The use of the core .