[about Modelsim simulation] design and Simulation of 4-bit counter

In fact, this article should be FPGA The first part of learning , The black gold used in the previous article AX301 Development board , But for a variety of reasons , Delayed in writing , Use here VScode Programming
VScode You can download it directly from Tencent computer manager, so I won't give you a link .
The installation and association of other software are not described here ,VScode After successful installation , You need to install some plug-ins ：

Mainly to explain Modelsim The simulation process , The principle of the counter will not be repeated here

Project_ex

ex Namely example It means

The purpose of creating this empty project file is simply to copy and paste it directly for future projects , By the way, let's talk about the function of each folder .
Doc： Used to store engineering instructions and circuit design documents
Ip_core: Store the called ip Nuclear documents （ For the time being ）
Quartus_prj: Engineering documents exist and state that the used for development is Quartus Software
Src： Store project source files
Sim： Deposit TB Simulation file

Verilog Code

Asynchronous reset is used here , Use VScode open Src Folder and create new .v file

module Counter_4Bits 
(
    input               clk,
    input               rst_n,
    
    output reg [3:0]    cnt_data
);

always @(posedge clk or negedge rst_n) begin
    if(!rst_n)
        cnt_data<=0;
    else if (cnt_data==4'b1111)
        cnt_data<=0;
    else
        cnt_data<=cnt_data+1'b1; 
end

endmodule

TB Documentation

Use VScode open Sim Folder and create new TB_Counter_4Bits.v file

`timescale 1ns/1ns
module TB_Counter_4Bits ();
    
reg clk;
reg rst_n;

wire [3:0] cnt_data;

initial begin
    clk<=1'b1;
    rst_n<=1'b0;
    #20
    rst_n<=1'b1;
end

always #10 clk=!clk;

Counter_4Bits _inst
(
    .clk(clk),
    .rst_n(rst_n),

    .cnt_data(cnt_data)
);


endmodule

The following is a combination of Modelsim Simulation analysis TB File code

newly build Modelsim Simulation Engineering

open Modelsim Software , top left corner File->New->Project, In the pop-up window , change Project Name by TB_Counter_4Bits And will Project Location Change to Sim Under the folder , And then click OK
Right click in the blank space of the interface Add to Project->Exiting File… take Sim Under folder TB File with the Src Under folder .v Add the file to the project , Pictured ：

Find... In the menu bar Compile->Compile All Click compile to find Simulate->Start Simulate Click to show ：

Point machine work Next to ＋ Number selection TB file ：

Never check it Enable optimization！
Never check it Enable optimization！
Never check it Enable optimization！
Never check it Enable optimization！
Never check it Enable optimization！
Never check it Enable optimization！
Never check it Enable optimization！
And then click OK
appear ：

stay Objects That is, in the upper right corner of the above figure “CTRL+A” after “CRTL+W” appear wave

stay wave Click on the + and x The middle one , such wave You can have a single window
stay wave Left side of window “CTRL+A” after “CTRL+G” Group the signals and click on the lower left corner

Find and enter the simulation time in the menu bar , Here I set it to 1000ns, Click the first one next to the simulation time box Run Or press F9


analysis ：
1） front 20nsrst_n The signal corresponds to low level TB This paragraph in the document

initial begin
    clk<=1'b1;
    rst_n<=1'b0;
    #20
    rst_n<=1'b1;
end

2）clk Every time the signal passes 10ns Flip once , Corresponding TB This paragraph in the document

always #10 clk=!clk;

3） It's written because 20ns Corresponding 50MHz, use verilog The code simulates a 50MHz The crystal of
4） When cnt_data Came to 4’b1111 In this state ,clk The rising edge of ,cnt_data It becomes 4‘b0000 state , There is such a sentence in the instantiation .cnt_data(cnt_data), Ahead cnt_data From Counter_4Bits.v This module in , In the back bracket cnt_data come from TB In file wire [3:0] cnt_data; this sentence . That is to say TB This variable in the file is the same as that in the source file cnt_data This variable is connected . The same is true for other statements in instantiation .
5） This is not an analysis , I mainly want to say that in the process of code writing, statements such as bit width type should be written , Variables are more standardized for the code written in this way , Then it is the key to write notes

summary

In fact, it should be FPGA Learn the first article in the series , As for the study of language itself, you can almost learn it by writing some simple combinational logic circuits and sequential logic circuits . The summer vacation is too bad to go on ……