Floating point addition and subtraction method of vivado IP core floating point

Vivado IP Core floating point addition and subtraction Floating-point

Catalog

Preface

One 、 Example of floating point addition and subtraction

Two 、 Configuration instructions

3、 ... and 、Floating-point IP Core configuration steps

Four 、 Simulation

1. Top level code

2. Simulation code

5、 ... and 、 Simulation analysis

summary

---

Preface

          With the continuous development of manufacturing technology , Field programmable logic gate array （FPGA） More and more integration , More and more applications , Among them, some mathematical processing classes must be used when processing digital signals IP nucleus . Recently, research on Spatial Adaptive Anti-jamming Technology is under way FPGA Hardware implementation , Some of them are inevitably used IP nucleus , Today from Floating point addition and subtraction So let's talk about that vivado In the middle of Floating-point This IP Nuclear bar , I hope it can help you in your study .

---

Tips ： The following is the main body of this article , All are original by the author , It's not easy to write an article , I hope you will attach a link to this article when reprinting .

One 、 Example of floating point addition and subtraction

        In order to facilitate the analysis of the results of the later simulation , Here we will give examples of floating-point addition and subtraction , The following example is directly used for simulation , Verify whether the simulation results are correct .

        example： Set floating point number a=32'b1100_0000_1101_0011_0011_0011_0011_0011, namely a=-6.6, Floating point numbers b=32'b0100_0001_0000_1100_1100_1100_1100_1101, namely b=8.8, be a+b=32'b0100_0000_0000_1100_1100_1100_1100_1110, namely a+b=2.2000003（ The reason is not equal to 2.2, Because the floating-point representation itself has a precision problem ）,a-b=32'b1100_0001_0111_0110_0110_0110_0110_0110, namely a-b=-15.4.

Two 、 Configuration instructions

        Because this time a Floating-point IP Nuclear realization can add and subtract , So there must be a control signal to control whether to add or subtract . This control signal is in the data book 6 Bit , But the specific generation IP Nuclear time actually has 8 position , The default configuration of the upper two digits is 0, The specific configuration is shown in the figure 1 Shown .

chart 1 Add / subtract configuration instructions

 

3、 ... and 、Floating-point IP Core configuration steps

          stay vivado Mid search Floating-point, To find the IP After the core, you can complete the corresponding configuration according to the following operations .

        1. First configuration Operation Selection Interface , Pictured 2 Shown .

chart 2 Operation Selection Interface configuration

         2. Next configuration Precision of Inputs Interface , Pictured 3 Shown .

chart 3 Precision of Inputs  Interface configuration

         3. Then configure Optimizations Interface , Pictured 4 Shown .

chart 4 Optimizations  Interface configuration

         4. Final configuration Interface Options Interface , Pictured 5 Shown .

chart 5 Interface Options  Interface configuration

          above 4 After all the interfaces are configured, you can click on the lower right corner OK Button generation IP nucleus .

Four 、 Simulation

1. Top level code

Build a top-level module , Name it float_add_sub, Used to instantiate the just generated IP nucleus .

The code is as follows ：

`timescale 1ns / 1ps
//
// Company: cq university
// Engineer: clg
// Create Date: 2022/07/23 12:19:25
// Design Name: 
// Module Name: float_add_sub
// Project Name: 
// Target Devices: 
// Tool Versions: 2017.4
// Description: 
// Dependencies: 
// Revision:1.0
// Revision 0.01 - File Created
// Additional Comments:
// 
//

module float_add_sub(
     input clk,
     input a_tvalid,
     input [31:0] a_tdata,
     input b_tvalid,
     input [31:0] b_tdata,
     input operation_tvalid,
     input [7:0] operation_tdata,
     output result_tvalid,
     output [31:0] result_tdata
    );
    
    float_add_sub_ip float_add_sub_ip_u1(
      .aclk(clk),
      .s_axis_a_tvalid(a_tvalid),
      .s_axis_a_tdata(a_tdata),
      .s_axis_b_tvalid(b_tvalid),
      .s_axis_b_tdata(b_tdata),
      .s_axis_operation_tvalid(operation_tvalid),
      .s_axis_operation_tdata(operation_tdata),
      .m_axis_result_tvalid(result_tvalid),
      .m_axis_result_tdata(result_tdata)
    );
    
endmodule

2. Simulation code

Build a simulation module , Name it float_add_sub_tb, It is used to simulate the instantiation of the top-level module just now IP nucleus .

The code is as follows ：

`timescale 1ns / 1ps
//
// Company: cq uiniversity
// Engineer: clg
// Create Date: 2022/07/23 12:34:59
// Design Name: 
// Module Name: float_add_sub_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 2017.4
// Description: 
// Dependencies: 
// Revision:1.0
// Revision 0.01 - File Created
// Additional Comments:
//

module float_add_sub_tb();
     reg clk;
     reg a_tvalid;
     reg [31:0] a_tdata;
     reg b_tvalid;
     reg [31:0] b_tdata;
     reg operation_tvalid;
     reg [7:0] operation_tdata;
     wire result_tvalid;
     wire [31:0] result_tdata;

float_add_sub u1_float_add_sub(
      .clk(clk),
      .a_tvalid(a_tvalid),
      .a_tdata(a_tdata),
      .b_tvalid(b_tvalid),
      .b_tdata(b_tdata),
      .operation_tvalid(operation_tvalid),
      .operation_tdata(operation_tdata),
      .result_tvalid(result_tvalid),
      .result_tdata(result_tdata)
);
always #5 clk=~clk;
   
initial begin
    clk=1'b0;
#10;     a_tvalid<=1'b1;
            a_tdata<=32'b1100_0000_1101_0011_0011_0011_0011_0011;
            b_tvalid<=1'b1;
            b_tdata<=32'b0100_0001_0000_1100_1100_1100_1100_1101;    
            operation_tvalid<=1'b1;
            operation_tdata<=8'b0000_0000;        // Add 
 #400;  a_tvalid<=1'b1;
            b_tvalid<=1'b1;
            operation_tvalid<=1'b1;
            operation_tdata<=8'b0000_0001;        // Subtraction 
end

always @(posedge clk) begin
        if (result_tvalid == 1'b1)  begin
            a_tvalid <=1'b0;
            b_tvalid<=1'b0;
           operation_tvalid <= 1'b0;
        end      
    end

endmodule

5、 ... and 、 Simulation analysis

         The simulation results are shown in the figure 6 Shown , Compare the examples of floating-point addition and subtraction listed above , It can be seen that this module successfully realizes the addition and subtraction of floating-point numbers .

chart 6 Simulation results

---

summary

  This time, I introduce How do you use it? vivado Medium Floating-point IP Verify the addition and subtraction of floating-point numbers .