[mit 6.s081] LEC 4: page tables notes

Lec 4: Page tables

• Ref: https://github.com/huihongxiao/MIT6.S081/tree/master/lec04-page-tables-frans
• Preparation: xv6 book Chapter 3

Outline

1. Address spaces address space
2. paging HW Support page table ( Virtual memory ) The related hardware
3. xv6 vm code+layout

Address Spaces

Strong isolation

Page Tables

summary

Used to create different address spaces for processes
from CPU and Memory management unit (Memory Management Unit, MMU) Realization
The page table is stored in memory , There are special registers to record its physical address . RISC-V In Chinese, it means SATP register .

MMU Used to complete the conversion from virtual address to physical address

Address partition

Page (page) Divide memory into units . RISC-V Middle page (page) by 4KB.
The virtual address is divided into index and offset Two parts . RISC-V in , Virtual address 64 position , The number of effective address digits is 39 bits : 27 position index, 12 position offset
Physical memory address 56 position : 44 Bit is the physical page number (Physical Page Number, PPN), 12 Bit is the intra page offset (offset)

RISC-V Page table implementation - Three level page table structure

• Virtual address : 64bit: 27bit Indexes (L2, L1, L0), 12bit Page offset
• Physical address : 64bit: 10bit Retain , 44bit Indexes ( Physical page number PPN), 10bit Sign a

27bit Of index Divided into 3 individual 9bit The index of (L2, L1, L0).
Divided into top-level page directory (Top Level Page Directory), Intermediate page directory (Middle Level Page Directory) and The lowest level page directory ( A page table ).
An entry in the page directory is called a page table entry (Page Table Entry, PTE), 8Bytes. A page directory 4KB, Yes 512 individual PTE. Every PTE There is 44bit PPN and 10 bit Flags. The physical address stored in the page directory (SATP The register is also a physical address ).
The top-level page directory consists of L2 Do the index , L1 Make an offset ; The intermediate page directory consists of L1 Do the index , L0 Make an offset .
Sign a :

• Valid: Express PTE Whether it works . Invalid indicates that it cannot be used to obtain the virtual address .
• Readable/Writable: Is it readable? / Write this page
• Executable: Whether the instructions in this page can be executed
• User: Whether the page can be accessed by processes in user space

Page table cache (TLB)

Page table cache (Translation Lookaside Buffer, TLB)
When switching page tables , TLB Will be emptied .
MMU and TLB It exists in every CPU Nuclear . According to the processor Cache Whether it is indexed by physical address , To decide on TLB After or before the address translation .
3 The level page table is implemented by hardware . MMU It's hardware . XV6 Medium walk() Function also implements the page table lookup function , Return a corresponding PTE. walk() The reasons why functions exist include : Used to set the initial page table for the operating system ; Used to copy data from kernel space to user space .

Kernel page table distribution

• notes : yes Page table of kernel

On the left is the virtual address space distribution of the kernel . The upper right is the physical memory space (DRAM), At the bottom right is I/O Device address space .

• boot ROM: Boot read-only memory . When the motherboard is powered on, it is initially executed , Boot and load the operating system .
• PLIC: Interrupt controller (Platform-Level Interrupt Controller)
• CLINT: Core Local Interruptor, Interrupt part . ( In the latest xv6 In the instruction , This part does not appear in the virtual address space )
• UART0: Universal Asynchronous Receiver/Transmitter, Copy and Console Interact with the monitor .
• VIRTIO disk: Interact with disk .

new edition xv6 Kernel address space distribution ( The difference is CLINT Part removed in virtual space ):

Kernel stack (Kstack) The corresponding physical address is mapped 2 Time , There was another time when Kernel data in . But usually use the top belt Guard page Of . Different processes have different kernel stacks .
Guard page Generally, it is not mapped to physical memory , Its PTE Of Valid Bit is not set , Used to judge whether the kernel stack is out of bounds .
In virtual memory "Free memory" Part will store the page table of the user process , text and data.

Virtual address space distribution of user process :

XV6 Page table code

kernel/main.c-main()
-> kvminit() Create page table
-> kvminithart() Set up SATP register , After that, all memory addresses are virtual addresses , Address translation starts