Some work experience after joining the digital ic design

First, the circuit framework and timing analysis of the code

The way of writing code in previous courses is relatively direct and casual. After generally understanding the design requirements, I start writing code without paying attention to the requirements of clock and reset. The sensitive variables of the always block are alsoAll kinds of latches are generated, and the generated latches are even more numerous. After writing, the code can run through the behavioral simulation and can be used on the development board, and the learning task of one semester is completed.

The disadvantages of this method are also significant: although the results of some codes in behavioral simulation are correct, their actual performance on the development board is not satisfactory.Various bugs appear.In the final analysis, the understanding of the code was not deep enough at that time, and there was no need to realize what kind of circuit these codes generated, and what kind of results such a circuit would cause.There will be no bugs of all kinds.Such techniques are also very practical in work. There are a lot of codes to be built in the future, the framework is very complex, and the sub-modules and top modules are stacked one by one.Timing analysis, it is very difficult to modify the code framework after encountering a bug in the later stage, and it is not conducive to us to understand the logic function of the entire circuit.Therefore, drawing circuit diagrams and waveform diagrams frequently is the first step to do a good job in front-end design.

The first counter circuit diagram drawn by the landlord after joining the job

Second, consider the practicality of the code from different angles

Digital chip design is a very time- and money-consuming industry. After the formed circuit is made into a mask and photoetched on the silicon wafer, it cannot be changed.Therefore, there are many factors and influences that need to be considered when designing the code.At the design point, the algorithm and function of the circuit implementation and the required resources must be planned first.After the design is completed, it must pass the verification and testing of the back-end.Therefore, when writing code, you should also consider the back-end timing analysis and STA.
For example, for a multi-bit counter, if the synchronous clock is used, the gate circuit device will be much more expensive than the asynchronous clock, but the asynchronous design is not used in the verilog HDL design.Because asynchronous sequential logic is difficult to control the competition and risk caused by combinational logic and delay, the more complex the circuit, the more difficult it is to debug the asynchronous design, and the trigger conditions of the asynchronous design are complex, and asynchronous changes may be triggered at any time, causingMetastability, etc.The most important thing is that asynchronous design will make back-end verification and STA (static timing analysis) extremely complicated. The back-end requires clock and reset (jump control signal) to be relatively pure, and too many sensitive variables.It will make it difficult for STA to proceed, so asynchronous design is generally not used.Similarly, the clock and reset signals and other variables are not allowed to do some logic operations, which will cause the clock or reset to be less pure.

Three, the means of debugging

After the code is written, behavior-level simulation must be performed. When viewing the waveform, it is inevitable that some parts do not meet the design requirements and need to be modified.But must not modify the standard framework of the circuit just to figure out the correct timing, for example: adding signals other than reset and clock difference to the sensitive list of the always block will also makeBackend validation work gets complicated.Or put the same signal in multiple always blocks to assign values.If this is the only way to meet the design requirements, then the initial design is definitely unreasonable, and we must try to find the problem from the design method itself.