Digital IC Design self-study ing

  Absolute zero basis ┭┮﹏┭┮

1、 Fundamentals of digital electronic technology

Learning video ：

University of China mooc  Digital electronic technology   Beijing University of science and technology

University of China moocVLSI Design basis （ Fundamentals of digital integrated circuit design ） Southeast University

2、 Learning the environment needed for chip development

Linux Environmental Science

• compiler ：Vim
• Scripting language ：tcl/python/perl
• makefile

Vim Study ：

  Reference video ：

vim Introductory tutorial （ common 3 speak ） The first month lights lanterns

makefile Study ： 

Reference blog ： 

How to write a Makefile file （ Teach you hand in hand ）_Wyatt_zhai The blog of -CSDN Blog _makefile Documentation

How to write a Makefile_ Ink long day blog -CSDN Blog _makefile How to write

Reference video ：

【c Language 】11. How to write Makefile file

EDA Tools ：

• VSC/Questasim Compile simulation
• Verdi    Visualization tools

vcs Step by step compilation simulation _hh199203 The blog of -CSDN Blog _vcs compile

Verdi Basic course _ Canghai Yisheng's blog -CSDN Blog _verdi

3、Verilog

The following divisions , It is divided according to your current feeling of learning , For reference only

primary —— understand Verilog  grammar

Learn the reference video ：

B standing  Verilog Zero Basics 、6 Hours to master Verilog grammar （Verilog Introduction to grammar ）

Learning content sorting ：（ Take your own notes according to the learning video ）

Verilog Basics （ according to HDLBits Arrangement ）

Verilog—— Inverter

Verilog—— NAND gate

Verilog—— Multiplexer logic design

Verilog—— Complement conversion

Verilog——7 Segment nixie tube decoder

Verilog—— Counter

Verilog—— Pseudo random code generator

Verilog—— Second counter

Verilog—— Add adjacent points and output

Verilog—— Triangular wave generator （ State machine ）

Verilog—— Serial data receiving （ State machine ）

Verilog—— Serial port data transmission （ State machine ）

Verilog—— Serial instruction processor （ State machine ）

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Understand in the middle Verilog The relationship between code and synthesis generation circuit ：

  University of China MOOC  Core power —— Hardware accelerated design method   （ Chapter two ）（ Explain Verilog And circuit design ）

Learning content sorting ：（ Take your own notes according to the learning video ）

 Verilog HDL Can be comprehensively described （ High-quality Verilog Writing ）

Comprehensive style —— stay RTL How to consider delay in writing 、 area 、 Power waste 、 wiring

RTL Design guidelines

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intermediate —— Small module learning

Learn the reference video ：

University of China MOOC Computer composition and CPU Design experiments  （ Use Verilog Examples of design ）

Learning content sorting ：（ Take your own notes according to the learning video ）

Elementary module  

Tristate gates and multiplexers

《 Computer composition and CPU Design experiments 》1 Combinatorial logic （ One ）

《 Computer composition and CPU Design experiments 》 experiment 1： The data selector is composed of three state gate and multiplexer

Encoding conversion （ Encoder 、 Decoder ） 

《 Computer composition and CPU Design experiments 》2 Combinatorial logic （ Two ）

《 Computer composition and CPU Design experiments 》 experiment 2 Seven segment decoder experiment

register （ Latch 、 trigger ）

《 Computer composition and CPU Design experiments 》3 Sequential logic （ One ）

《 Computer composition and CPU Design experiments 》 experiment 3： Register group （ Pile up ) experiment

shift register

《 Computer composition and CPU Design experiments 》3 Sequential logic （ Two ）

 《 Computer composition and CPU Design experiments 》 experiment 4： Water lamp and shift register experiment

Counter 、 Frequency divider

 《 Computer composition and CPU Design experiments 》4 Sequential logic （ 3、 ... and ）

《 Computer composition and CPU Design experiments 》 experiment 5 Experiment of counter and frequency divider

State machine

《 Computer composition and CPU Design experiments 》5 Finite state machine Verilog HDL describe （Finite State Machine,FSM）

《 Computer composition and CPU Design experiments 》 experiment 6 Color lamp controller experiment

Class entry module

Addition and subtraction circuit

《 Computer composition and CPU Design experiments 》 experiment 7 Addition and subtraction circuit

Arithmetic logic unit

《 Computer composition and CPU Design experiments 》 experiment 8 arithmetic logic unit (ALU)

Data access

《 Computer composition and CPU Design experiments 》 experiment 9 Single cycle data path experiment

Memory

《 Computer composition and CPU Design experiments 》 experiment 10 Memory experiments

Hardwired control

senior —— Large module  

CPU Design

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