Clock tree analysis example

1） The frequency divider's timing check

Long tree In principle, you only need to balance the clock of the same frequency

The following example , Where the frequency divider is located reg With its master clock sink Between timing check, Pictured 1.

chart 1

div_1 or div_2 And FF3 There are timing check, Theoretically, it will not appear unless the front-end design deliberately makes it difficult for the back-end engineers div_1、div_2 And FF1、FF2 Of timing check, Well understood. , such skew Too large timing is difficult to converge , This kind of problem cannot be taken into account when synthesizing . So most common problems are div_1/div_2 And FF3 Between setup or hold Violation .

terms of settlement :

1、CTS Stage , Rewrite a sdc, Give Way div_1 and div_2 As create_clock First long tree, And let two clock do balance, Then read the original sdc, Grow over tree Part of the setup dont touch, Give the master clock a long tree Let it go div_1/div_2 And FF3 do balance.

2、postroute Stage , hold FF3 Anterior superfluous CKBUF/CKINV Delete , If you use ICC Words ,ICC Long tree It's from back to front , Do it first clock gate To sink pin, And then from clock root To clock gate, So it's like FF3 such CTS The first thing to do is very short , And then with others sink balancce To insert buffer/inverter, There will be many pockets here buffer/inverter, Deletion will not affect clock transition.

 

To be continued ...