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[sequential logic circuit] - counter

2022-07-24 16:43:00 【Li Yuchen】

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Welcome to learn digital circuit —— Sequential logic circuit .
Here we will talk about binary counters 、 Decimal counter and integrated counter 74LS161, I hope that through our study, you will better understand the mystery of digital circuits .

Catalog

One 、 Counter

1. Binary counter

（1） Asynchronous binary addition counter

（2） Synchronous binary addition counter

2. Decimal counter

（1） Circuit composition

（2） working process

3. Integrated counter

（1）74LS161 Pin arrangement and graphic symbols of the chip

One 、 Counter

A digital circuit that can accumulate the number of input pulses is called a counter , Counter is a unit logic circuit widely used in digital circuits , Except directly used as technology 、 frequency division 、 Out of time , It is also often used in digital instruments 、 Program control 、 In the fields of computers and so on .

There are many kinds of counters ,

① The carry system by count is different , It can be divided into binary 、 Decimal and N Binary counter, etc ;

② Press the increment of the value in the counter 、 Reduce the situation , It can be divided into addition counters 、 Subtraction counter 、 Reversible counter ;

③ According to the different state transition time of each trigger in the counter , It can be divided into synchronous counter and asynchronous counter .

1. Binary counter

Definition ：

Under the action of counting pulse , The digital circuit that counts the state transition of each trigger according to the binary coding law is called Binary counter .

The core device that constitutes the counter circuit has the counting function JK trigger . Can be JK The trigger is connected to the counting state , As shown in the figure ：

（1） Asynchronous binary addition counter

As shown in the figure, the circuit uses three JK Trigger connected asynchronism 3 Bit binary addition counter .

Of triggers in the figure $\overline{R_{D}}$ Terminated together as a direct reset input signal to the counter ; The counting pulse is added to the lowest trigger Of FF0 End , Other triggers CP Receive low trigger in turn Q End control . When each trigger receives a negative jump pulse signal, the state will flip .

The waveform is shown in the figure ：

working process ：

Before counting , At the reset end $\overline{R_{D}}$ First input a negative pulse , send $Q_{2}Q_{1}Q_{0}$ =000, This process is called clearing , After clearing , Should make $\overline{R_{D}}$ =1, To count normally .

When the first counting pulse CP After action , The falling edge of the pulse causes the trigger FF0 Of $Q_{0}$ from 0 State to 1 state , The other two triggers have no CP The function of the falling edge , Still hold 0 state , So when the first CP After action , The counter status is $Q_{2}Q_{1}Q_{0}$ =001.

When the second counting pulse CP When it works , trigger FF0 Flip , $Q_{0}$ from 1 State to 0 state , $Q_{0}$ The falling edge of is added to FF1 Clock input of , send $Q_{1}$ from 0 State to 1 state , $Q_{1}$ The rising edge changes to the trigger FF2 Invalid , $Q_{2}$ The state remains the same , So when the second CP After action , The counter status is $Q_{2}Q_{1}Q_{0}$ =010.

And so on , Be the seventh CP The counter status is 111, Be the eighth CP After the action, the counter returns to 000 state , Complete a counting cycle .

（2） Synchronous binary addition counter

As shown in the figure, synchronization 3 Bit binary addition counter ：

Trigger of all levels CP End to end , Controlled by the same clock pulse , Obviously, the flip-flop state of each trigger is synchronized with the clock , Therefore calls Synchronous counter .

2. Decimal counter

The structure of binary counter is simple , Easy to calculate . But on many occasions , Using decimal counter is more in line with people's habits . The so-called decimal counter is a digital circuit that counts the state conversion of each trigger under the action of counting pulse according to the coding law of decimal number .

The method of expressing decimal numbers with binary numbers is called Two — Decimal code （ namely BCD code ）. Decimal numbers have 0~9 common 10 Number , At least use 4 Bit binary number . and 4 Bit binary numbers have Sixteen States , Express 1 Decimal numbers only need ten states , So we need to remove six of them . It is often used in decimal counters 8421BCD Code encoding method for counting .

8421 The code is shown in table ：

（1） Circuit composition

The asynchronous decimal addition counter circuit is composed of 4 Bit binary counter and a gate circuit for clearing the counter , The main difference with binary addition counter is that it skips binary digits 1010~1111 Of 6 Status .

（2） working process

Counter input 0~9 When counting pulses , Working process and 4 Bit binary asynchronous counters are exactly the same , After the ninth counting pulse $Q_{3}Q_{2}Q_{1}Q_{0}$ =1001.

When the tenth counting pulse arrives , The counter status is $Q_{3}Q_{2}Q_{1}Q_{0}$ =1010, here $Q_{3}=Q_{1}=1$ , NAND gate input all 1, Output is 0, Reset each trigger , namely $Q_{3}Q_{2}Q_{1}Q_{0}$ =0000, At the same time, the NAND gate output becomes 1, The counter starts working again . So as to achieve 8421BCD Code decimal The function of adding and counting .

3. Integrated counter

The integrated counter integrates the trigger and the closed circuit on a chip , Easy to use and expand . There are many types of medium scale integrated synchronous counters , common 4 Bit decimal synchronous counter has 74LS160、74LS162、74LS196、CC40192 etc. ;4 Bit binary synchronous counter has 74LS161、74LS163、74LS169、74LS191 etc. .

（1）74LS161 Pin arrangement and graphic symbols of the chip

74LS161 The pin arrangement and graphic symbols of the chip are shown in the figure ：

① Asynchronous reset

When asynchronously set 0 Control terminal $\overline{CR}$ =0 when , Regardless of the state of other inputs , With or without clock pulses , The counter output will be set directly to zero , It is called asynchronous zeroing .

② Sync preset number

When $\overline{CR}$ =1 when , Synchronous setting control terminal $\overline{LD}$ =0, And in CP When the rising edge acts , The parallel input data is placed at the output of the counter , send $Q_{3}Q_{2}Q_{1}Q_{0}$ = $D_{3}D_{2}D_{1}D_{0}$ . Because this operation is related to CP Sync , So it is also called synchronous preset .

The truth table is shown in the table ：

③ keep

at that time $\overline{CR}$ = $\overline{LD}$ =1、 $CT_{T}\cdot CT_{P}=0$ when , Output $Q_{3}Q_{2}Q_{1}Q_{0}$ remain unchanged . Then if $CT_{P}$ =0、 $CT_{T}$ =1, Then carry output signal CO remain unchanged ; if $CT_{P}$ =1、 $CT_{T}$ =0, Carry output signal CO Low level .

④ Count

When $\overline{CR}$ = $\overline{LD}$ = $CT_{T}$ = $CT_{P}$ =1 when ,CP When the rising edge is valid , Realize the function of adding and counting .

【 Sequential logic circuit 】 It's over , In the next issue, we will open a new chapter ——【 Generation and transformation of pulse waveform 】

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