Axi protocol (2): five channels and two transactions of Axi architecture

5 AXI Five channels and two transactions of the architecture

5.1 Five channels

stay AXI There are five channels in the architecture , From the perspective of reading and writing, they can be divided into two groups （AR,R;AW,W,B）, From the perspective of data and address control, they can be divided into （R,W;AR,AW;B）：

• Read address channel （read address channel）AR
• Read data channel （read data address channel）R
• Write address channel （write address channel）AW
• Write data channel （write data channel）W
• Write response channel （write response channel）B

explain 1： read / Write address channel （AR AW）

Both read and write transactions have their own address channels , This address channel carries the address and control information necessary for the transmission transaction .

Read the address / Control and write address / Control channels （AR AW）： Two channels （ Corresponding to their respective reading or writing processing ） It's actually transmitting , Need to put （ Read or write ） Address of data storage and corresponding control information .

So just to emphasize here , In fact, only the address of the first byte of data is passed , That's the starting address , The address to be read or written later changes according to the control information （ It can be temporarily understood that different control information will have different address iteration methods , It may not change, it may increase by an equal amount ）.

explain 2： read / Write data channel （R W）

read / In the write data channel, I want to read / Data written

read / Write data channels all include one LAST The signal , Used to indicate a transaction （） The last data transmitted .

R The data bus of can be 8,16,32,64,128,256,512,1024bits, It should also be noted that the read response signal is included in the read data channel , Different from the write response channel . The read data channel is transmitted from slave To master Read data and read response information . The read response information indicates the completion status of the read transaction . This is why there is no read response channel （ I'll study this later ZZQ）

The write data channel carries master Need to write slave The data on the , In the same way, we can use 8,16,32,64,128,256,512,1024bits Bus bit width . Write data path transmission master towards slave Of writing data . Every eight data will have one byte lane , Used to indicate which... On the data bus byte It works .

explain 3： Write response channel B

The write response channel provides a way for devices to respond to write transactions . Require all write processing to return a response . The last sentence means , Each burst reading and writing of the response signal in the channel will produce a .

5.2 read / Write business （transcation）

AXI There are two kinds of transactions , They are read transactions and write transactions .

read / Write the schematic diagram of the transaction in the channel

Description of these two figures

• Address channel （AR and AW）： The data transmitted in these two channels are address information and control information , These messages represent the other two corresponding data channels R perhaps W Some characteristics of real data in , For example, address information is used to put the location of these real data , The control information indicates how the data should be placed , Or the enabling of these data 、 Storage and so on
• Write data channel （W） The data sent by the master device can be written to the slave device , When write processing occurs , The slave device will respond through the write channel （B） Tell the master device about the completion of this write behavior . Empathy , Read data channel （R） It means that the slave device sends the data to be read to the master device , There is no separate read response channel during read processing , Read response this operation is in （AR） Read the address