how to use xilinx's FFT ip

FFT解释

FFT（Fast Fourier Transform,快速傅立叶变换）是离散傅立叶变换的快速算法,也是我们在数字信号处理技术中经常会提到的一个概念.在大学的理工科课程中,After completing a course in advanced mathematics,Digital signal processing is generally studied as a professional basic course for communication electronics majors,The reason is that it involves a lot of theoretical derivation of advanced mathematics,At the same time, it is the theoretical basis of various applied technologies.

为什么需要FFT？

FFT(快速傅立叶变换)是离散傅立叶变换的快速算法.

傅立叶变换的物理意义在哪里？

傅立叶原理表明：任何连续测量的时序或信号,都可以表示为不同频率的正弦波信号的无限叠加.而根据该原理创立的傅立叶变换算法利用直接测量到的原始信号,以累加方式来计算该信号中不同正弦波信号的频率、振幅和相位.当然这是从数学的角度去看傅立叶变换.
Then look at the Fourier transform from a physical point of view,It actually helps us to change the traditional method of analyzing signals in the time domain to the thinking of analyzing problems from the frequency domain,The following three-dimensional figure can help us better understand this angle conversion：

所以,最前面的时域信号在经过傅立叶变换的分解之后,变为了不同正弦波信号的叠加,我们再去分析这些正弦波的频率,可以将一个信号变换到频域.有些信号在时域上是很难看出什么特征的,但是如果变换到频域之后,就很容易看出特征了.这就是很多信号分析采用FFT变换的原因.另外,FFT可以将一个信号的频谱提取出来,这在频谱分析方面也是经常用的.
傅立叶变换提供给我们这种换一个角度看问题的工具,看问题的角度不同了,问题也许就迎刃而解！

如何使用xilinx的FFT ip实现FFT过程

In this article, we mainly focus on the data sourcefft再到ifft的过程,Thereby verifying whether the whole process function is available;

matlab准备生成iq数据

clc;
clear all;
close all;

fs = 250e6;     % adc采样率
fout = 10e6;    % 生成信号频率
len = 1024;     % 生成信号长度
t = 0:1/fs:(len-1)/fs;  % 采样点的时间片
amp = 25000;    % adc信号幅度

adc_dat = exp(j*2*pi*fout*t); % adc数据
adc_dat = awgn(adc_dat, 40);% 对生成信号加入噪声

adc_dat_i = round(real(adc_dat)*amp);% 量化adc数据
adc_dat_q = round(imag(adc_dat)*amp);% 量化adc数据

% 画出信号的时域和频域图
subplot(211);
plot(adc_dat_i);hold on;
plot(adc_dat_q);
title('信号时域图');
xlabel('采样点');
ylabel('信号幅度');
subplot(212);
fft_adc_dat = adc_dat_i+j*adc_dat_q;
fft_data = abs(fft(fft_adc_dat, len));
fft_data = fftshift(fft_data);
fft_data = 20*log10(fft_data);
fft_data = fft_data - max(fft_data);
x = linspace(-fs/2,fs/2,len);
plot(x, fft_data);
title('信号频谱图');
xlabel('信号频率MHz');
ylabel('信号功率');
% 存储ADC数据
adc_dat = [adc_dat_q;adc_dat_i];
u_adc_dat = sign2com(adc_dat, 16);
fp = fopen('adc_dat.bin', 'w');
fprintf(fp, '%04x%04x\n',u_adc_dat);
fclose all;

xilinx的fft ip设置

xilinx的ifft ip设置

ifftneed to configurebit置为0,and change the input data bit width under,其他与fft配置一致;

verilog代码仿真

`timescale 1ns/1ps

module testbench;

reg										clk						;
reg										rst						;
reg		[11:0]							dat_cnt					;
reg		[31:0]							s_data_tdata			;
reg										s_data_tvalid			;
reg		[31:0]							adc_dat[1023:0]			;

wire									s_data_tlast			;
wire									s_data_tready			;
wire	[63:0]							m_data_tdata			;
wire	[15:0]							m_data_tuser			;
wire									m_data_tvalid			;
wire									m_data_tready			;
wire									m_data_tlast			;
wire	[79:0]							m_ifft_data_tdata		;
wire	[15:0]							m_ifft_data_tuser		;
wire									m_ifft_data_tvalid		;
wire									m_ifft_data_tready		;
wire									m_ifft_data_tlast		;

always #5.00	clk = ~clk	;

initial	begin
	clk=0;
	rst=1;
	#200
	rst=0;
end

localparam					LEN	=	1024			;

initial	begin
	$readmemh("./matlab/adc_dat.bin", adc_dat, 0, LEN-1);
end

[email protected](posedge clk)
begin
	if(rst)	begin
		s_data_tdata	<=0;
		s_data_tvalid	<=0;
		dat_cnt			<=0;
	end
	else	begin
		if(dat_cnt<LEN)	begin
			if(s_data_tready)	begin
				dat_cnt			<=dat_cnt+1;
				s_data_tdata	<=adc_dat[dat_cnt];
				s_data_tvalid	<=1;
			end
			else	begin
				s_data_tvalid	<=0;
			end
		end
		else if(s_data_tready)	begin
			s_data_tvalid	<=0;
		end
	end
end

assign	s_data_tlast = ((dat_cnt==1024)&&s_data_tvalid)? 1 : 0;

xfft_0 u_xfft_0 (
	.aclk								(clk						), // input wire aclk
	.aresetn							(~rst						), // input wire aresetn
	.s_axis_config_tdata				(8'd1						), // input wire [7 : 0] s_axis_config_tdata
	.s_axis_config_tvalid				(1'b1						), // input wire s_axis_config_tvalid
	.s_axis_config_tready				(							), // output wire s_axis_config_tready
	.s_axis_data_tdata					(s_data_tdata				), // input wire [31 : 0] s_axis_data_tdata
	.s_axis_data_tvalid					(s_data_tvalid				), // input wire s_axis_data_tvalid
	.s_axis_data_tready					(s_data_tready				), // output wire s_axis_data_tready
	.s_axis_data_tlast					(s_data_tlast				), // input wire s_axis_data_tlast
	.m_axis_data_tdata					(m_data_tdata				), // output wire [63 : 0] m_axis_data_tdata
	.m_axis_data_tuser					(m_data_tuser				), // output wire [15 : 0] m_axis_data_tuser
	.m_axis_data_tvalid					(m_data_tvalid				), // output wire m_axis_data_tvalid
	.m_axis_data_tready					(m_data_tready				), // input wire m_axis_data_tready
	.m_axis_data_tlast					(m_data_tlast				), // output wire m_axis_data_tlast
	.event_frame_started				(							), // output wire event_frame_started
	.event_tlast_unexpected				(							), // output wire event_tlast_unexpected
	.event_tlast_missing				(							), // output wire event_tlast_missing
	.event_status_channel_halt			(							), // output wire event_status_channel_halt
	.event_data_in_channel_halt			(							), // output wire event_data_in_channel_halt
	.event_data_out_channel_halt		(							) // output wire event_data_out_channel_halt
);

xifft_0 u_xifft_0 (
	.aclk								(clk						), // input wire aclk
	.aresetn							(~rst						), // input wire aresetn
	.s_axis_config_tdata				(8'd0						), // input wire [7 : 0] s_axis_config_tdata
	.s_axis_config_tvalid				(1'b1						), // input wire s_axis_config_tvalid
	.s_axis_config_tready				(							), // output wire s_axis_config_tready
	.s_axis_data_tdata					(m_data_tdata				), // input wire [63 : 0] s_axis_data_tdata
	.s_axis_data_tvalid					(m_data_tvalid				), // input wire s_axis_data_tvalid
	.s_axis_data_tready					(m_data_tready				), // output wire s_axis_data_tready
	.s_axis_data_tlast					(m_data_tlast				), // input wire s_axis_data_tlast
	.m_axis_data_tdata					(m_ifft_data_tdata			), // output wire [79 : 0] m_axis_data_tdata
	.m_axis_data_tuser					(m_ifft_data_tuser			), // output wire [15 : 0] m_axis_data_tuser
	.m_axis_data_tvalid					(m_ifft_data_tvalid			), // output wire m_axis_data_tvalid
	.m_axis_data_tready					(1'b1						), // input wire m_axis_data_tready
	.m_axis_data_tlast					(m_ifft_data_tlast			), // output wire m_axis_data_tlast
	.event_frame_started				(							), // output wire event_frame_started
	.event_tlast_unexpected				(							), // output wire event_tlast_unexpected
	.event_tlast_missing				(							), // output wire event_tlast_missing
	.event_status_channel_halt			(							), // output wire event_status_channel_halt
	.event_data_in_channel_halt			(							), // output wire event_data_in_channel_halt
	.event_data_out_channel_halt		(							)  // output wire event_data_out_channel_halt
);

endmodule

仿真结果