手撕Verilog PWM呼吸灯

pwm的频率通过parameter传递，
对clk按 （分频参数+1）进行分频，
占空比从0增加到 分频参数/(分频参数+1)

rtl

module pwm#(
	parameter [10:0] FREQUENCY = 11'd4
)(
    input clk,
    input rst_n,
    
	output  pwm
    );
    
	reg [10:0] freq;
	reg [10:0] duty;

    always @(posedge clk ) begin
		if(!rst_n)
			freq <= 11'd0;
		else if(freq == FREQUENCY) begin
			freq <= 11'd0;
		end
		else begin
			freq <= freq + 1'b1;
		end
	end

	always @(posedge clk ) begin
		if(!rst_n)
			duty <= 11'd0;
		else if(freq == FREQUENCY) begin
			if(duty < FREQUENCY)
				duty <= duty + 1'b1;
			else
				duty <= 11'd0;
		end
	end

	assign pwm = (freq < duty)? 1'b1: 1'b0;

endmodule

tb

module tb_pwm(

    );
	parameter CYCLE = 10;
	reg clk;
	reg rst_n;

	wire pwm;


	initial begin
		clk = 1'b0;
		rst_n = 1'b0;
		#20 rst_n = 1'b1;
	end

	always #(CYCLE/2) clk = ~clk;


	pwm u1(
		.clk(clk),
		.rst_n(rst_n),
		.pwm(pwm)
	);


endmodule

仿真结果