Introduction to testbench

This is a testbench Simple example .

`timescale 1ns/1ps

module tb_top();

//-------------------------------------------------------
reg sys_clk_100mhz;
reg sys_clk_200mhz;
reg sys_clk_400mhz;

reg rst;
reg wen;
reg ren;

reg [ 9:0] addra ;
reg [31:0] dina  ;
reg [ 9:0] addrb ;
wire[31:0] doutb ;
//-------------------------------------------------------


//-------------------------------------------------------
always #5    sys_clk_100mhz = ~sys_clk_100mhz;
always #2.5  sys_clk_200mhz = ~sys_clk_200mhz;
always #1.25 sys_clk_400mhz = ~sys_clk_400mhz;
//-------------------------------------------------------


//-------------------------------------------------------
    bram_i32o32_d1024 bram_i32o32_d1024 (
        .clka                           ( sys_clk_400mhz               ),// input wire clka
        .wea                            ( wen                          ),// input wire [0 : 0] wea
        .addra                          ( addra                        ),// input wire [9 : 0] addra
        .dina                           ( dina                         ),// input wire [31 : 0] dina
        .clkb                           ( sys_clk_400mhz               ),// input wire clkb
        .addrb                          ( addrb                        ),// input wire [9 : 0] addrb
        .doutb                          ( doutb                        ) // output wire [31 : 0] doutb
    );

//-------------------------------------------------------


//-------------------------------------------------------
initial begin

sys_clk_100mhz = 1'b0 ;
sys_clk_200mhz = 1'b0 ;
sys_clk_400mhz = 1'b0 ;
rst            = 1'b1 ;
wen            = 1'b0 ;
ren            = 1'b0 ;
addra          = 0;
addrb          = 0;
dina           = 0;

#10
rst            = 1'b0 ;

#100
wen            = 1'b1 ;
addra          = 0;
dina           = 0;

#2.5
wen            = 1'b1 ;
addra          = 1;
dina           = 1;

#2.5
wen            = 1'b1 ;
addra          = 2;
dina           = 2;

#2.5
wen            = 1'b1 ;
addra          = 3;
dina           = 3;

#2.5
wen            = 1'b0 ;
ren            = 1'b1 ;
addra          = 0;

#2.5
wen            = 1'b0 ;
ren            = 1'b1 ;
addra          = 1;

#2.5
wen            = 1'b0 ;
ren            = 1'b1 ;
addra          = 2;

#2.5
wen            = 1'b0 ;
ren            = 1'b1 ;
addra          = 3;

#2.5
wen            = 1'b0 ;
ren            = 1'b0 ;

end
//-------------------------------------------------------


endmodule

Make a clock

 Use initial sentence ----------

reg clock;
initial begin
    clock=0;
    forever #10 clock=~clock;
end


 Use always sentence ---------------

reg clock;
initial
    clock=0;
always
    #10 clock=~clock;

Reference resources

1、 author	post
	Verilog Of testbench introduction