SystemVerilog syntax

Preface

Sort out the basic grammar used in the work .

1、 data type

Two state data type , That is, only 0 1 Two states , No, x z, It is beneficial to improve the performance of the simulator , Reduce memory usage .

Writing testbench in ,bit Variables of type can be used for assignment operations or wiring , That is, it is also used for things similar to reg、wire The function of .

 Basic data type 
  time          64 An integer , The default unit is seconds 
  real           come from Verilog, as C Of double type ,64 position 
  shortreal      come from C Of float type ,32 position 
  string         Variable length character array 
  void           Empty return , For functions 

 Integer data type 
--- The default is signed number 
  shortint      16 An integer               ,2 state （1,0） The default value is 0
  int           32 An integer               ,2 state （1,0） The default value is 0
  longint       64 An integer               ,2 state （1,0） The default value is 0
  byte          8 An integer （ASCII character ）   ,2 state （1,0） The default value is 0
  integer       32 An integer               ,4 state （0、1、X、Z） The default value is x

--- The default is unsigned number 
  bit           0 or 1                  ,2 state （1,0） The default value is 0
  reg            come from Verilog           ,4 state （0、1、X、Z） The default value is x
  logic          And reg similar              ,4 state （0、1、X、Z） The default value is x

2、task

task And function There are two big differences

（1）task You can add time-consuming statements , and function Don't waste time ( This is related to verilog identical ).

（2）task You can call task and function, and function Can only call function.

One more thing to remind novices ：

task and function Can't be used in initial and always Of

 

3、 Time delay

＃100;

Reference resources

1、 author	post
gsithxy	[SV]SystemVerilog Grammatical summary
	SystemVerilog—— data type
	SystemVerilog—Timescale analysis

Reference resources