LCD parameter interpretation and calculation

https://blog.csdn.net/longxiaowu/article/details/24319933
Linux Kernel amba lcd Controller use clcd_panel The structure represents a LCD Hardware parameters of the screen ：

/* include/linux/fb.h */
struct fb_videomode {
    
const char *name; /* optional */
u32 refresh; /* optional */
u32 xres;
u32 yres;
u32 pixclock;
u32 left_margin;
u32 right_margin;
u32 upper_margin;
u32 lower_margin;
u32 hsync_len;
u32 vsync_len;
u32 sync;
u32 vmode;
u32 flag;
};
/* include/linux/amba/clcd.h */
struct clcd_panel {
    
struct fb_videomode mode;
signed short width; /* width in mm */
signed short height; /* height in mm */
u32 tim2;
u32 tim3;
u32 cntl;
unsigned int bpp:8,
fixedtimings:1,
grayscale:1;
unsigned int connector;
};

Let's look at an example ：http://lxr.linux.no/linux+v2.6.37.4/arch/arm/mach-lpc32xx/phy3250.c

fb_videomode The meaning of each parameter
Linux Yes LCD The abstract of is shown in the following figure ：

Let's study fb_videomode The meaning of each member ：

 Linux Kernel amba lcd Controller use clcd_panel The structure represents a LCD Hardware parameters of the screen ：

   
    

     
 
      
 
       
 
      
 
      
 
       
 
        /* include/linux/fb.h */ 
       
 
      
     
 
      
 
       
 
      
 
      
 
       
 
        struct fb_videomode {
          
       
 
      
     
 
      
 
       
 
      
 
      
 
       
 
        const 
        char *name; 
        /* optional */ 
       
 
      
     
 
      
 
       
 
      
 
      
 
       

         u32 refresh; 
        /* optional */ 
       
 
      
     
 
      
 
       
 
      
 
      
 
       

         u32 xres; 
       
 
      
     
 
      
 
       
 
      
 
      
 
       

         u32 yres; 
       
 
      
     
 
      
 
       
 
      
 
      
 
       

         u32 pixclock; 
       
 
      
     
 
      
 
       
 
      
 
      
 
       

         u32 left_margin; 
       
 
      
     
 
      
 
       
 
      
 
      
 
       

         u32 right_margin; 
       
 
      
     
 
      
 
       
 
      
 
      
 
       

         u32 upper_margin; 
       
 
      
     
 
      
 
       
 
      
 
      
 
       

         u32 lower_margin; 
       
 
      
     
 
      
 
       
 
      
 
      
 
       

         u32 hsync_len; 
       
 
      
     
 
      
 
       
 
      
 
      
 
       

         u32 vsync_len; 
       
 
      
     
 
      
 
       
 
      
 
      
 
       

         u32 sync; 
       
 
      
     
 
      
 
       
 
      
 
      
 
       

         u32 vmode; 
       
 
      
     
 
      
 
       
 
      
 
      
 
       

         u32 flag; 
       
 
      
     
 
      
 
       
 
      
 
      
 
       

         }; 
       
 
      
     
 
      
 
       
 
      
 
      
 
       
 
        /* include/linux/amba/clcd.h */ 
       
 
      
     
 
      
 
       
 
      
 
      
 
       
 
        struct clcd_panel {
          
       
 
      
     
 
      
 
       
 
      
 
      
 
       
 
        struct fb_videomode mode; 
       
 
      
     
 
      
 
       
 
      
 
      
 
       
 
        signed 
        short width; 
        /* width in mm */ 
       
 
      
     
 
      
 
       
 
      
 
      
 
       
 
        signed 
        short height; 
        /* height in mm */ 
       
 
      
     
 
      
 
       
 
      
 
      
 
       

         u32 tim2; 
       
 
      
     
 
      
 
       
 
      
 
      
 
       

         u32 tim3; 
       
 
      
     
 
      
 
       
 
      
 
      
 
       

         u32 cntl; 
       
 
      
     
 
      
 
       
 
      
 
      
 
       
 
        unsigned 
        int bpp: 
        8, 
       
 
      
     
 
      
 
       
 
      
 
      
 
       

         fixedtimings: 
        1, 
       
 
      
     
 
      
 
       
 
      
 
      
 
       

         grayscale: 
        1; 
       
 
      
     
 
      
 
       
 
      
 
      
 
       
 
        unsigned 
        int connector; 
       
 
      
     
 
      
 
       
 
      
 
      
 
       

         }; 
       
 
      
    
   
    

Let's look at an example ： http://lxr.linux.no/linux+v2.6.37.4/arch/arm/mach-lpc32xx/phy3250.c

fb_videomode The meaning of each parameter

Linux Yes LCD The abstract of is shown in the following figure ：

Let's study fb_videomode The meaning of each member ：

name	Abbreviation in the data book	Chinese name	significance	remarks
name	No	name	LCD name （ Optional ）	No
refresh	No	refresh frequency	refresh frequency （ Many examples in the kernel are assigned to 60）	No
xres	No	Line width	Number of pixels per row	No
yres	No	Screen height	The number of lines on the screen	No
pixclock	No	Pixel clock	The length of each pixel clock cycle , The unit is picosecond （10 Negative 12 In the second place 1 second ）	No
left_margin	HBP (Horizontal Back Porch)	Horizontal trailing edge	An image to be inserted at the beginning of the output of pixel data in each row or column Prime clock cycles	No
right_margin	HFP (Horizontal Front Porch )	Horizontal frontier	At the end of each row or column of pixels LCD Line clock output pulse The number of pixel clocks between	No
upper_margin	VBP (Vertical Back Porch)	Vertical trailing edge	The number of invalid lines at the beginning of the frame after the vertical synchronization period	No
lower_margin	VFP (Vertical Front Porch)	Vertical leading edge	From the end of data output of this frame to the beginning of vertical synchronization cycle of the next frame Number of invalid lines before	No
hsync_len	HPW (HSYNC plus width)	Row synchronization pulse width	Company ： Pixel clock cycle	There are also manuals called HWH(HSYNC width)
vsync_len	VPW (VSYNC width)	Vertical synchronous pulse width	Company ： Show the time of one line th	There are also manuals called VWH(VSYNC width)
sync	No	Synchronous polarity setting	It can be set as needed FB_SYNC_HOR_HIGH_ACT( Horizontal synchronization high level is active ) and FB_SYNC_VERT_HIGH_ACT( Vertical sync high active )	No
vmode	No	No	Most of the examples in the kernel are set directly to FB_VMODE_NONINTERLACED.interlaced It means to interlace ［ Interlace ］ scanning , Used in TV 2:1 Interleaving rate of , That is, each frame is divided into two fields , Two vertical scans , Scan odd rows in one field , Another field scans even lines . Obviously LCD This is not the current model .	No
flag	No	No	We haven't seen the usage at present	No

explain ：

(1)Linux Yes LCD The abstraction of is image centric , and LCD The manual centers on the synchronization signal , So in the kernel left_margin Means before each line （ The front naturally corresponds to the left ） Number of idle cycles , And it corresponds to LCD Horizontal trailing edge in data book （HBP Horizontal Back Porch）, It refers to the idle period after the line synchronization signal . The references are different , But it's the same thing .

(2) The horizontal synchronization signal is sometimes called the line synchronization model , Vertical synchronization signal is called field synchronization signal .

(3) about LCD Of frambuffer For the abstract model, please refer to the documentation in the kernel ：Documention/fb/frambuffer.txt.

(4)fb_videomode The purpose of each member is to refer to the... In the kernel code include/linux/amba/clcd.h Medium clcdfb_decode() Function summary , There is no guarantee that the protection is absolutely correct .

clcd_panel The meaning of each member

clcd_panel yes ARM Of AMBA LCD Controller specific data structures , It's defined in include/linux/amba/clcd.h in .

ARM Of AMBA LCD The controller data manual is here ： http://infocenter.arm.com/help/topic/com.arm.doc.ddi0121d/DDI0121.pdf

width and height Its unit is mm, It should refer to the physical size of the screen . But in drivers/video/amba-clcd.c Is simply given to fb.var.width/height, Most of the examples in the kernel are directly assigned to -1.

from include/linux/amba/clcd.h Medium clcdfb_decode() Functions and drivers/video/amba-clcd.c Medium clcdfb_set_par() The function shows tim2 Is the clock and signal polarity register ,tim3 Is the end of line control register , It is used to control whether a pulse is output after each line of output .tim3 Generally don't care , Use the default value .tim2 Generally according to LCD The data book uses the following macros to assign values ：

#define TIM2_CLKSEL (1 << 5) choice LCD The clock source of ,0 Select the on-chip clock ,1 Select the clock for external pin access . Generally, you can use the default value
#define TIM2_IVS (1 << 11) Reverse vertical synchronization The polarity of the signal .0: High active , Low level invalid .1： contrary
#define TIM2_IHS (1 << 12) Reverse horizontal synchronization The polarity of the signal .0： High active , Low level invalid .1： contrary
#define TIM2_IPC (1 << 13) To select whether the pixel data is driven to... On the rising or falling edge of the display clock LCD cable .0： Rising edge .1： Falling edge .
#define TIM2_IOE (1 << 14) This bit selects the effective polarity of the output enable signal .0: High active , Low level invalid .1： contrary
#define TIM2_BCD (1 << 26) Set this bit to 1, Make PCD The frequency division of is invalid . It is mainly used for TFT display . This bit is usually not set , Use the default value 0.

clcd_panel Of cntl Members are actually written to AMBA LCD Control register of the controller , Depending on the hardware, use the following macro to populate ：

#define CNTL_LCDEN (1 << 0) LCD Enable control bit .0： prohibit .1： Can make .
#define CNTL_LCDBPP1 (0 << 1) bit[1-3] Define color depth .bpp：bits per pixel, Number of bits per pixel .000 = 1 bpp.

#define CNTL_LCDBPP2 (1 << 1) 001 = 2 bpp.
#define CNTL_LCDBPP4 (2 << 1) 010 = 4 bpp.
#define CNTL_LCDBPP8 (3 << 1) 011 = 8 bpp.
#define CNTL_LCDBPP16 (4 << 1) 100 = 16 bpp 
#define CNTL_LCDBPP16_565 (6 << 1) 110 = 16 bpp, 5:6:5 mode
#define CNTL_LCDBPP24 (5 << 1) 101 = 24 bpp (TFT panel only).
#define CNTL_LCDBW (1 << 4) STN LCD monochrome / Color selection .1： colour ,0： monochrome
#define CNTL_LCDTFT (1 << 5) LCD display TFT Type selection .0： STN display , Use the grayscale .1: TFT display , Do not use a grayscale scaler
#define CNTL_LCDMONO8 (1 << 6) This bit determines monochrome STN LCD It's using 4 Bit parallel interface or 8 Bit parallel interface .0:4 Bit interface .
#define CNTL_LCDDUAL (1 << 7) STN single LCD Display or dual LCD Display selection .0＝ Single screen
#define CNTL_BGR (1 << 8) Color mode selection ,0＝RGB： Normal output ,1＝BGR： Red and blue swap positions
#define CNTL_BEBO (1 << 9) Control the storage order of bytes in memory ： 0＝ Small endian byte order ,1＝ Big endian byte order
#define CNTL_BEPO (1 << 10) Set how pixels are sorted ,0＝ Small end pixel sorting ,1＝ Use large pixel sorting
#define CNTL_LCDPWR (1 << 11) LCD Power enable .1＝LCD The display is powered on and LCDV[23:0] Signal enable
#define CNTL_LCDVCOMP(x) ((x) << 12) LCD Vertical comparison is interrupted .00＝ The vertical sync pulse is active ,01＝ Start at the vertical back edge ,10＝ Valid video image start ,11＝ The vertical leading edge begins
#define CNTL_LDMAFIFOTIME (1 << 15) DMA FIFO Request delay
#define CNTL_WATERMARK (1 << 16) LCD DMA FIFO Waterline .0： When DMA FIFO contain 4 Or 4 When there are more than units above, a LCD DMA request .1:8 individual .

Generally, initialization is required  CNTL_LCDBPP16_565、 CNTL_LCDTFT、CNTL_BGR、CNTL_LCDVCOMP(x) .CNTL_LCDEN and CNTL_LCDPWR Will be driven to set automatically .

CNTL_LCDVCOMP(x) It is usually initialized to CNTL_LCDVCOMP(1).

clcd_panel Of bpp Members are passed to frambuffer Subsystem . It feels like this place is a little repetitive ,cntl We already have this information in .

bpp It's usually 16 perhaps 24.

clcd_panel Other members of the did not see the specific usage .

How to go from LCD Calculation parameters in the data book

As follows: 16BPP Of TFT Screen as an example . yes , we have LCD A list of parameters will be given , For example, below , You can clearly find the required parameters in the red box , take “type” Typical values are sufficient . But there are LCD There is no such list directly , Setting some parameters is not given , This needs to be determined through the sequence diagram .

The following is Tianma's 3.5 " TFT LCD screen TM035KDH03 For example .

Parameter calculation ：

You can see LCD The clock is 28M, therefore pixclock=1000000/28

The line synchronization pulse width is one clock cycle , therefore ,hsync_len=1

The width of the field synchronization pulse is one line period , therefore vsync_len = 1

The above figure is the display sequence diagram of a frame of image . The figure above shows ,up_margin = 13-1=12,, yres= 240,

The whole field period is 263, therefore lower_margin= 263-13-240 = 10

See at the same time , The high level of the column synchronization signal is valid , The line synchronization signal is also active at high level .

The above figure is a one line sequence diagram .

You can see ,left_margin = 69, xres = 320, right_margin = 408 -320 - 70 = 18

The data is valid on the rising edge , The output enable is active at high level .

Sum up the above parameters , The results are as follows ：

     
      

       
 
        
 
         
 
        
 
        
 
         
 
          static 
          struct clcd_panel conn_lcd_panel = {
            
         
 
        
       
 
        
 
         
 
        
 
        
 
         

           .mode = { 
         
 
        
       
 
        
 
         
 
        
 
        
 
         

           .name = 
          "QVGA TM035KDH03", 
         
 
        
       
 
        
 
         
 
        
 
        
 
         

           .refresh = 
          60, 
         
 
        
       
 
        
 
         
 
        
 
        
 
         

           .xres = 
          240, 
         
 
        
       
 
        
 
         
 
        
 
        
 
         

           .yres = 
          320, 
         
 
        
       
 
        
 
         
 
        
 
        
 
         

           .pixclock = 
          35714, 
         
 
        
       
 
        
 
         
 
        
 
        
 
         

           .left_margin = 
          69, 
         
 
        
       
 
        
 
         
 
        
 
        
 
         

           .right_margin = 
          18, 
         
 
        
       
 
        
 
         
 
        
 
        
 
         

           .upper_margin = 
          12, 
         
 
        
       
 
        
 
         
 
        
 
        
 
         

           .lower_margin = 
          10, 
         
 
        
       
 
        
 
         
 
        
 
        
 
         

           .hsync_len = 
          1, 
         
 
        
       
 
        
 
         
 
        
 
        
 
         

           .vsync_len = 
          1, 
         
 
        
       
 
        
 
         
 
        
 
        
 
         

           .sync = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, 
         
 
        
       
 
        
 
         
 
        
 
        
 
         

           .vmode = FB_VMODE_NONINTERLACED, 
         
 
        
       
 
        
 
         
 
        
 
        
 
         

           }, 
         
 
        
       
 
        
 
         
 
        
 
        
 
         

           .width = 
          -1, 
         
 
        
       
 
        
 
         
 
        
 
        
 
         

           .height = 
          -1, 
         
 
        
       
 
        
 
         
 
        
 
        
 
         

           .tim2 = 
          0, 
         
 
        
       
 
        
 
         
 
        
 
        
 
         

           .cntl = ( CNTL_LCDTFT | CNTL_LCDVCOMP( 
          1) | CNTL_LCDBPP16_565), 
         
 
        
       
 
        
 
         
 
        
 
        
 
         

           .bpp = 
          16, 
         
 
        
       
 
        
 
         
 
        
 
        
 
         

           };