Fpga/cpld final examination paper for the first semester of Nanjing University of information technology 2020-2021

One 、 Completion  ( Every empty 1 branch , common 20 branch )

1、 The abstract level description includes 4 layer , Namely     Behavior level    、   Data flow   、    Gate level    And switch level .

2、 A variable is a quantity whose value can be changed during the running of a program . There are two kinds of variables , One type is    Wire network   type , It generally indicates the physical connection of the hardware circuit , The other is    Register type   Corresponding to the storage element with the function of state keeping .

3、Verilog Four value logic system is adopted 0 Indicates low level ,1 High level ,x Express    Uncertain value    Z Express    High resistance      .

4、 According to the output logic, state machines can be divided into two types , One is called   miller   State machine , The output of its sequential logic depends not only on the current state , It also depends on the input ; The other is called    Mole   The output of the sequential logic of the state machine sequence only depends on the current state .

5、 stay Verilog A number that usually indicates the number of digits in a language , Please calculate and complete the following equation ：

8’d120 = 8’h  78    = 8’b 01111000

6、Verilog There are three types of ports for ：   input   、   output   、  inout  .

7、 Equivalence operators include logical equality and case equal , if A=4’b1010,B=4’b1101,C= 4'blxxz, D= 4 b1xxz, E=4'b1xxx, be A==C As the result of the Boolean value x,A==B As the result of the Boolean value 0,C===D As the result of the Boolean value 1.

8、 The splice operator can splice multiple operands together , if A=1’b1,B=2’b00,c=2’b10, be

Y={A , B, C, 3’b001} As the result of the   9’b10010001 

Y={4{A},2{B},C} As the result of the   10’b1111000010 

9、 In order to implement the task at the same time ,Verilog By means of task Add before keyword   automatic   keyword , Implement automatic tasks .

Two 、 choice question ( Each question 2 branch , common 20 branch )

1、 stay Verilog HDL In the logic operation of , set up A=8’b11010001,B=8’b00011001, Expression “A&B” As the result of the     A 

A. 8’b00010001 B. 8’b11011001C. 8’b11001000D. 8’b00110111

2、`timescale Used to describe time scales , sentence `timescale lns/10ps What is the simulation accuracy in the program   C  

A. 1ns B.1psC. 10psD. 10ns

3、 If the cardinality is not specified in the number description , The default value is decimal . If no positioning width is specified , The default bit width is related to the emulator and the computer used （ The minimum is   C   position ）

A. 8 B.16C. 32D. 64

4、Verilog HDL Defines a series of reserved words , It's called keyword , Indicate which of the following is not a keyword (  B  )

A. input B.WireC. beginD. task

5、 When the port has no data type defined , The default is type   B  

A. reg B. wire C. tri D. Unavailable

6、 The register type remains until a new value is assigned   D  

A. 0B. 1C. X D. Original value

7、 From the inside of the module , The input port should be   A  

A.  Wire mesh type B. Register type C. Wire net or register type D. None of the above is true

8、 From the outside of the module , The input port should be   C  

A.  Wire mesh type B. Register type C. Wire net or register type D. None of the above is true

9、 Because the network type represents the physical connection line , So it does not store logical values , Must be driven by the device . When one wire When a type of signal is not driven , The default value is   D  

A. 0B. 1C. XD. Z

10、 For modules module fulladd(sum, cout, a, b, cin) Come on , Use the named port connection method , Which of the following methods can call the module   D  

A. fulladd f4(sum, cout, a, b, cin)

B.fulladd f4(SUM, COUT, A, B, CIN)

C. fulladd f4(.SUM(sum), .COUT(cout), .A(a), .B(b), .CIN(cin))

D. fulladd f4(.sum(sum), .cout(cout), .a(a), .b(b), .cin(cin))

3、 ... and 、 Q & A questions ( Each question 4 branch , common 20 branch )

1、Verilog The calling of modules in the design should comply with the port connection rules , Please elaborate on the details of this rule .

Input port ： From the inside of the module , Input port must be network data type , From the outside of the module , The input port can be connected to the network or reg Data type variables

Output port ： From the inside of the module , The output port can be a network or reg data type , From the outside of the module , The output must be connected to a network type variable , Cannot connect to reg Variable of type .

Input / Output ： From the inside of the module , Input / The output port must be of network data type , From the outside of the module , Input / The output port must also be connected to the network type variable .

Bit width matching ：Verilog Allow the inner and outer parts of the port to have different bit widths .

Port not connected ： Allow the port of the module instance to remain unconnected .

2、 What are the characteristics of continuous assignment and procedure assignment statements ？ Simply analyze the difference between the two statements .

The continuous assignment statement is Verilog The basic statement of data flow modeling , It is used to assign values to the network , It is equivalent to gate level description , However, the circuit is described from a higher abstract point of view , Consecutive assignment statements must be in the form of the keyword assign Start

The update object of procedure assignment statement is register , Integers , Real numbers or time variables , These types of variables are assigned , Its value will remain unchanged , Until a new value is assigned by another procedure assignment statement .

Consecutive assignment statements are always active , The change of any operand will lead to the re evaluation and re assignment of the expression , But procedure assignment statements only work when they are executed .

3、 There are two types of block statements ： Sequential block and parallel block , Please describe the characteristics of both .

The statements in a sequential block are executed sequentially one after the other , Only after the execution of the previous statement , To execute the following statements （ Except for non blocking assignment statements with built-in delay control ） If the statement includes a delay or event control , Then the delay is always relative to the simulation time of the execution completion of the previous statement .

Statements in parallel blocks execute concurrently , The order in which statements are executed is determined by the delay or event control in the respective statements , The delay or event control in the statement is relative to the moment when the block statement begins to execute .

4、 stay Verilog in , Tasks and functions are different , Please summarize the differences between the two .

Mission ： It can support multiple purposes , Can calculate multiple result values , These result values can only be output through the output of the called task or the bus port . Ability to start other tasks or functions . There can be no or more variables of any type . no return value . Tasks can define their own simulation time units .

function ： Respond to the value of the input signal by returning a value , Generally, functions are used as operators in expressions , The result of this operation is the return value of this function . Cannot start task . At least one input variable is required . There is a return value . Function simulation —— The simulation time is zero .

5、 Please explain the following nouns , Give Chinese explanation and English full name

HDL： Hardware description language Hardware Description Language

RTL： Register transfer level Register Transfer Level

FPGA： Field programmable  Field Programmable Gate Arrays

VLSI： vlsi Very Large Scale Integrated

EDA： Electronic design automation Electronic Design Automation

3、 ... and 、 Program questions   ( common 40  branch )

1、 It is known that D The module of the trigger is described as D_FF（q, d, clk, clr）, Please follow the figure below T Design description of trigger （ With complete Verilog Design blocks to implement ）.（5 branch ）

module T_FF(q,clk,reset);

output q;

input clk,reste;

wire d;

D_FF dff0(q,d,clk,reset);

not nl(d,q);

endmodule

2、 Use... According to the following figure Verilog The gate modeling method of language is realized SR Latch . At the same time, write the design block （SR_latch） And excitation block （Top）.（5 branch ）

module SR_latch（Q,Qbar,Sbar,Rbar）;
output Q,Qbar;
input Sbar,Rbar;
nand nl（Q,Sbar,Qbar）;
nand nl（Qbar,Rbar,Q）;
endmodule
module Top;

wire q,Qbar;
reg set,reset;
SR_latch ml(q,qbar,~set,~reset);

3、 Read the following program , Draw the sequence diagram of the program ( Include x,y,a,b,m).（5 branch ）

module stimulus
reg x,y, a,b,m;
initial
m=1’b0;
initial
begin 
#5 a=1’b1
#25 b=1’b0;
end
initial
begin
#10 x=1’b0;
#25 y=1’b1;
end
initial
#50 finish
endmodule

4、 Read the following program to answer the question （5 branch ）

reg [3:0] encoding：

integer state;

case(encoding)

4’b1xxx : next_state = 3;

4’bx1xx : next_state = 2;

4’bxx1x : next_state = 1;

4'bxxx1 : next_state = 0;

default : next_state = 0：

endcase

If input encoding The value of is 4’b10xz,next_state How much? ？  3

If input encoding The value of is 4’b00xz,next_state How much? ？  0

5、 Please use behavior level modeling to design one out of four selector . Note that the bit width of the selector input and output is 2 position . Just implement the design block .（5 branch ）

module mux4_to_l （out,i0,il,i2,i3,sl,s0）.

6、 Design asynchronous reset with behavior level , Synchronous set four digit counter .clear Reset on rising edge ,N_set Falling edge time setting , Values for N_in.（5 branch ）

module counter（Q, clock, clear, N_set, N_in）

7、 Please follow the state diagram below , Write Verilog State machine module , among In Input ,out For export , When the input meets the condition （S0,S1,S2） Realize state transition , If the condition is not satisfied, the state is maintained . Implement a complete design block program （ Note the input / output bit width ）.（10 branch ）

module fsm(clk, rst, ina,out);
input clk,rst, ina; // Define the clock 、 Reset and input signals 
output out; // Define the port that outputs the control signal 
reg out; // Define the status register 
parameter s0 = 3'b00,s1 =3'b01,
s2 =3'b10, s3=3'b11; // Define state variable parameter values 
reg [0:1] state;
always @ (posedge clk or negedge rst)
if (!rst)
begin // Define the initial state and output value after reset 
state<=s0;
out =0;
else
case(state)
s0:begin state<=(ina)?s1:s0;out=0;end
s1:begin state<=(ina)?s2:s0;out=0;end
s2:begin state<=(ina)?s3:s0;out=0;end
s3:begin state<=(ina)?s3:s0;out=1;end
endcase
end
endmodule