[digital ic/fpga] data accumulation output

Title Description ： Realize the cumulative output of serial input data , Input end input 8bit data , Whenever the module receives 4 After inputting data , Output end output 4 Cumulative result of received data . The interaction between input end and output end and upstream and downstream adopts valid-ready Two way handshake system . It is required that both upstream and downstream can At full speed transmission , No bubbles in data transmission , No additional performance loss due to the design of this module .
The interface of the circuit is shown in the figure below .valid_a Used to indicate data entry data_in The effectiveness of the ,valid_b Used to indicate data output data_out The effectiveness of the ;ready_a Used to indicate whether the module is ready to receive upstream data ,ready_b Indicates whether the downstream is ready to receive the output data of this module ;clk It's a clock signal ;rst_n It is an asynchronous reset signal .

Code

`timescale 1ns / 1ps
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